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L64777 dvb qam modulator order number i14031.a technical manual june 2000
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?cer of lsi logic corporation. document db14-000121-01, first edition, june 2000. this document describes revision a of the lsi logic corporation L64777 dvb qam modulator and will remain the of?cial reference source for all revisions of this product until rescinded by an update. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright ? 2000 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, g10, and the g10 logo design, are trademarks or registered trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies.
preface iii preface this book is the primary reference and technical manual for the L64777 dvb qam modulator. it contains a complete functional description for the L64777 and includes complete physical and electrical speci?cations for the L64777. audience this document assumes that you have some familiarity with digital video broadcasting, qam modulators, and related support devices. the people who bene?t from this book are: engineers and managers who are evaluating the modulator for possible use in a system engineers who are designing the modulator into a system organization this document has the following chapters and appendixes: chapter 1, introduction , introduces the L64777 dvb qam modulator. chapter 2, modulator architecture , describes the functional components of the L64777. chapter 3, interfaces , describes the L64777 interfaces. chapter 4, register descriptions , describes the registers used to con?gure and monitor the L64777. chapter 5, signals , presents the signal de?nitions for the L64777.
iv preface chapter 6, speci?cations , presents the electrical and timing speci?cations for the L64777. it also presents the pinout and packaging information. appendix a, programming the L64777 in serial host interface mode , discusses how to program the L64777 internal registers and data tables in serial host interface mode. appendix b, pll divider settings and l64724/34 connection , lists the pll divider settings for typical applications. it also describes the L64777 connection to the l64724. appendix c, monitoring device internal signals , describes how to program test register (14) for monitoring of device internal signals. related publications digital broadcasting systems for television sound and data services: framing structure, channel coding and modulation cable systems ets 300 429, september 1996. generic coding of moving pictures and associated audio , iso/iec 13818-1, mpeg2 systems, november 1994. g10 ? -p cw900100 10-bit direct digital synthesis digital-to-analog converter, preliminary datasheet , lsi logic, september 1998. l64724 satellite receiver technical manual, lsi logic, april 2000, order number i14030. conventions used in this manual the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre?x 0x for example, 0x32cf. binary numbers are indicated by the pre?x 0b for example, 0b0011.0010.1100.1111.
contents v contents chapter 1 introduction 1.1 overview 1-1 1.2 operating environment 1-2 chapter 2 modulator architecture 2.1 introduction 2-2 2.2 pll modes 2-4 2.2.1 pll mode 1 2-4 2.2.2 pll mode 2 2-5 2.3 i/o 2-6 2.3.1 input 2-6 2.3.2 output signals 2-6 2.3.3 control interface 2-8 2.3.4 serial microprocessor interface 2-10 2.4 input synchronization 2-10 2.4.1 sync acquisition phase 2-13 2.4.2 sync tracking phase 2-14 2.5 fifo clock conversion 2-16 2.6 sync/ef reinsertion unit 2-17 2.6.1 sync insertion mode 2-18 2.6.2 error flag insertion 2-18 2.6.3 energy dispersal (scrambler) unit 2-18 2.7 reed-solomon encoder 2-20 2.7.1 forward error correction (fec) 2-21 2.7.2 error handling and correction 2-22 2.8 convolutional interleaver 2-23 2.9 bytes to m-tuples converter 2-24 2.10 differential encoder and qam mapping 2-26 2.11 square root nyquist filter 2-27
vi contents 2.11.1 filter setup procedure 2-29 2.11.2 example 2-30 2.11.3 default filter characteristics 2-34 2.12 global control and pll module 2-34 2.12.1 numerically controlled oscillator (nco) 2-35 2.12.2 acquisition phase using the frequency measurement unit 2-36 2.12.3 autoacquisition mode 2-38 2.12.4 regulation phase 2-39 2.13 interpolator 2-39 2.14 serial microprocessor interface 2-40 2.15 test unit 2-41 chapter 3 interfaces 3.1 transport interface 3-1 3.1.1 synchronization 3-1 3.1.2 synchronization methods 3-2 3.1.3 transport error indicator handling 3-2 3.2 serial control interface 3-2 3.3 analog output interface 3-3 3.4 digital output interface 3-6 chapter 4 register descriptions 4.1 group 2 general-purpose registers 4-1 4.1.1 register 0 4-4 4.1.2 register 1 4-4 4.1.3 register 2 4-5 4.1.4 register 3 4-5 4.1.5 register 4 4-6 4.1.6 register 5 4-6 4.1.7 register 6 4-7 4.1.8 registers 7 and 8 4-8 4.1.9 registers 9 and 10 4-8 4.1.10 register 11 4-9 4.2 nco-related registers 4-10 4.2.1 register 12 4-10 4.2.2 register 13 4-11
contents vii 4.2.3 register 14 4-12 4.2.4 register 15 4-13 4.2.5 registers 16, 17, and 18 4-13 4.2.6 registers 19 and 20 4-13 4.2.7 registers 21 and 22 4-14 4.2.8 registers 23 and 24 4-14 4.2.9 register 25 4-14 4.2.10 registers 26, 27, and 28 4-14 4.2.11 registers 29, 30, and 31 4-15 4.2.12 registers 32, 33, and 34 4-15 4.2.13 registers 35, 36, and 37 4-15 4.2.14 registers 38 and 39 4-16 4.2.15 register 40 4-16 4.2.16 register 41 4-16 4.2.17 register 42 4-17 4.2.18 register 43 4-17 chapter 5 signals 5.1 overview 5-1 5.2 mpeg transport stream multiplexer signals 5-3 5.3 status information signals 5-4 5.4 test signals 5-5 5.5 control signals 5-6 5.6 external pll signals 5-6 5.7 analog qam signals 5-7 5.8 serial microprocessor interface signals 5-8 chapter 6 speci?cations 6.1 ac/dc speci?cations 6-1 6.1.1 electrical ratings 6-1 6.1.2 ac timing diagrams for L64777 6-3 6.2 pin descriptions and lists 6-5 6.2.1 L64777 electrical pin descriptions 6-5 6.2.2 numerical pin list for the L64777 6-8 6.2.3 alphabetic pin list for the L64777 6-9 6.3 package pinout 6-10
viii contents appendix a programming the L64777 in serial host interface mode a.1 serial bus protocol overview a-1 a.2 programming the slave address using the serial bus interface a-4 a.3 write cycle using the serial bus interface a-4 a.4 read cycle using the serial bus interface a-5 a.5 limitations a-7 appendix b pll divider settings and l64724/34 connection b.1 overview b-1 b.2 pll driver settings for typical applications b-2 b.3 connecting the L64777 to the lsi logic l64724 b-3 appendix c monitoring device internal signals customer feedback figures 1.1 L64777 operating environment 1-2 2.1 ets 300 429-compliant modulation operation 2-2 2.2 data path 2-3 2.3 phase and frequency detection with an external vco 2-5 2.4 analog i/q output interface diagram 2-7 2.5 required relation of iclk and din/dvalidin 2-9 2.6 fifo clock conversion 2-12 2.7 sync acquisition phase 2-13 2.8 sync tracking phase 2-14 2.9 fifo pointer concept 2-16 2.10 transport error flag insertion 2-18 2.11 scrambler basic serial architecture 2-19 2.12 shift register initialization sequence 2-19 2.13 code word structure 2-21 2.14 forward error correction data path 2-22 2.15 interleaver block diagram 2-23 2.16 symbol cutting from bytes 2-25
contents ix 2.17 byte to symbol conversion 2-25 2.18 differential encoder and qam mapping 2-26 2.19 pulse shaper structure 2-27 2.20 output scaling by arithmetic shift right 2-29 2.21 square-root raised cosine filter 2-34 2.22 nco loop diagram 2-36 2.23 frequency acquisition loop overview 2-38 2.24 serial bus base address 2-40 3.1 analog i/q output interface diagram 3-4 3.2 i and q dac filter diagrams 3-5 5.1 logic symbol for the L64777 5-2 6.1 ts input timing 6-3 6.2 L64777 reset timing diagram 6-3 6.3 L64777 bus 3-state delay timing 6-4 6.4 package 120-pin pqfp pinout 6-10 6.5 120-pin pqfp (pe) mechanical drawing 6-11 a.1 quick overview of the serial bus a-2 a.2 serial bus write/read cycle a-3 a.3 general call structure a-4 a.4 burst write to slave (master-transmitter, slave-receiver) a-5 a.5 single read from slave a-7 b.1 catv block diagram b-1 b.2 signals between the l64724 and L64777 b-3 tables 2.1 allocation of coef?cient-bits for phase 0 2-30 2.2 default nyquist filter coef?cients 2-32 4.1 group 2 bit allocation 4-2 4.2 reset values for register fields 4-17 6.1 L64777 absolute maximum ratings 6-2 6.2 L64777 recommended operating conditions 6-2 6.3 L64777 dc characteristics 6-2 6.4 L64777 preliminary timing parameters 6-4 6.5 L64777 pin description summary 6-5 6.6 L64777 numerical pin list 6-8 6.7 L64777 alphabetical pin list 6-9 b.1 typical settings of cnt_i and cnt_o b-2
x contents
L64777 dvb qam modulator technical manual 1-1 chapter 1 introduction this chapter provides an introduction to the L64777. it consists of the following sections: section 1.1, overview, page 1-1 section 1.2, operating environment, page 1-2 1.1 overview the L64777 chip implements a qam modulator that is digital video broadcasting (dvb)-compliant, as described in document ets 300 429. the input is an mpeg-2 system layer-compliant transport stream either in parallel byte-wide or serial format. the chip contains digital signal processing functions, digital-to-analog converters, and sampling clock circuitry that generates a quadrature amplitude modulation (qam)- modulated output signal in baseband. users can con?gure the device by means of its serial interface. the L64777 chip design is based on the existing lsi logic l64767 device and includes the following major enhancements: two internal digital-to-analog converters generate in-phase and quadrature (i and q) baseband signals. an on-chip voltage-controlled oscillator improves the symbol rate pll to support most frequently used application ranges. a serial interface replaces the eight-bit microprocessor interface. a digital numerically controlled oscillator (nco) and interpolation mode support operation with the l64724 device.
1-2 introduction 1.2 operating environment the modulator is intended to follow either an mpeg transport stream source (for example, a transport multiplexer) or a satellite receiver, such as the lsi logic l64724 (see figure 1.1). it processes mpeg-2 system- compliant frames at the input. you can program the sync word and block length, and the chip can reinsert the sync information. the device handles the mpeg-speci?c transport-packet error indication (tei) bit internally. figure 1.1 L64777 operating environment the features of the L64777 include: dvb standard ets 300 429-compliant modulation operation highly integrated global synchronization and clock control on-chip vco to support symbol rates up to 10 msymbols/s digital nco and interpolation mode to support operation with the l64724 four-fold nyquist ?lter oversampling maskable interrupts for all error conditions individual module bypass con?guration modes i and q baseband outputs both in digital and analog formats i 2 c-compatible serial interface for control, setup, and monitoring of various chip parameters user-controllable input synchronization schemes 16, 32, 64, 128, and 256 qam modes reed-solomon encoder mpeg transport mux qpsk satellite receiver L64777 qam cable network rf modulator transmission network mixer mpeg transport stream (digital) analog qam modulated i and q components
operating environment 1-3 frame sync byte reinsertion input jitter handling and reed-solomon gap insertion by a 128-word circular fifo buffer ieee 1149.1 jtag interface for testing up to 10 mbytes/s parallel data input up to 60 mbits/s serial data input up to 11.25 mbaud operation in nco mode of operation easy interface to most input sources 85 ?c ambient operation without special cooling devices unconstrained serial mode to allow modulation of non-mpeg data stream
1-4 introduction
L64777 dvb qam modulator technical manual 2-1 chapter 2 modulator architecture this chapter brie?y introduces the standard modulator chain and the architecture the device uses to implement the chain. this chapter consists of the following sections: section 2.1, introduction, page 2-2 section 2.2, pll modes, page 2-4 section 2.3, i/o, page 2-6 section 2.4, input synchronization, page 2-10 section 2.5, fifo clock conversion, page 2-16 section 2.6, sync/ef reinsertion unit, page 2-17 section 2.7, reed-solomon encoder, page 2-20 section 2.8, convolutional interleaver, page 2-23 section 2.9, bytes to m-tuples converter, page 2-24 section 2.10, differential encoder and qam mapping, page 2-26 section 2.11, square root nyquist filter, page 2-27 section 2.12, global control and pll module, page 2-34 section 2.13, interpolator, page 2-39 section 2.14, serial microprocessor interface, page 2-40 section 2.15, test unit, page 2-41
2-2 modulator architecture 2.1 introduction the L64777 implements the modulator processing chain de?ned in ets 300 429. this processing chain is illustrated in figure 2.1. figure 2.1 ets 300 429-compliant modulation operation figure 2.2 is a block diagram of the L64777 architecture. the input clock drives only the input synchronizing stage. the oclk, which is four times the qam symbol rate, is the base of all residual processing. a numerically controlled oscillator (nco) module allows the L64777 to interface with lsi logic l64724. in this case, the chip must receive the l64724 pclk clock; thus, the byte_clock output from l64724 must be applied to iclk. this assumes the pclk has generated the byte clock. energy dispersal rs (204,188) encoder convol. interleaver qam mapping byte to m-tuple conversion differential encoder i q square root nyquist filter
introduction 2-3 figure 2.2 data path 8 8 rs (204,188) encoder convol. interleaver & qam mapping byte to m-tuple global control and synchronization - start/stop signals generation iclk serial microprocessor interface oclk 1 data square root nyquist filter circular i q diff. encoder input sync energy dispersal 8 scan chain jtag test rambist sync & fifo error ?ag reinsertion stage buffer symbol clock generation pll (incl. vco and phase and freq. comp.) scl sda oclk inter- polator* pclk nco* dac dac i q * only used in pll mode 2 10 divided iclk & freq compare 128 8 8 8 10 10 10 m q i word
2-4 modulator architecture the qam mapping supports 16, 32, 64, 128, and 256 qam. the input to the device is an mpeg-2 compliant transport stream; its output consists of baseband qam signals in i and q. 2.2 pll modes connecting the L64777 to a satellite receiver and the lsi logic satellite decoder chip set requires the pll circuits to lock the input and output clocks. two modes can achieve this: mode 1 uses the phase/frequency detector and the dividers of L64777 to accept an external vco. mode 2 connects the pclk output of l64724 or l64734 to the L64777 pclk clock input, and connects the byte clock output to the iclk input of the L64777. this is also called the numerically controlled oscillator (nco) mode of operation. this mode is dedicated to the connection of the l64724 (see appendix b, pll divider settings and l64724/34 connection). set the pll_mode[1:0] pins to the values shown on page 5-6. do not change it during operation. 2.2.1 pll mode 1 figure 2.3 shows the phase and frequency detection for an external voltage-controlled oscillator (vco) loop. choose between frequency and phase detection through the microprocessor interface.
pll modes 2-5 figure 2.3 phase and frequency detection with an external vco prescalers (cnt_i) and a divider (cnt_o) in the feedback loop of the pll generate the internal operating clock (oclk). program the 15-bit prescalers through the microprocessor interface, selecting values for cnt_i and cnt_o that minimize cnt_o and reach the required ratio. 2.2.2 pll mode 2 in mode 2, the pclk input provides an external clock. the L64777 uses the internal nco to lock to the transport byte clock, provided at iclk. the chip generates an oclk internally. select pclk to be at least twice the frequency of the internal oclk. appendix b, pll divider settings and l64724/34 connection , describes the connection between the L64777 and the l64724 in mode 2 operation. consecutive sync blocks can have any gap length between them. thus, the L64777 can convert an input block to a block with a gap for rs insertion, as long as the size of the 128-byte circular input buffer is suf?cient to insert rs gaps and to cope with possible pll jitter. for an encoder with 16-parity rs insertion, the L64777 selects the size of the circular input buffer with suf?cient margin. when operating on public synchronous networks (such as the synchronous digital hierarchy, sdh, or plesiochronous digital hierarchy, pdh), the system designer must consider possible jitter on the input network. the design of the L64777 permits short-term deviations of input-to-output frequency of 56 bytes before a fifo overrun condition occurs. this is suf?cient for operations on sdh or pdh networks. oclk iclk +z - current load value load value cnt_o cnt_i frequency detect phase detect freq_phase_comp (from microprocessor) 2 2 from vco to vco pll_cs %2 %2
2-6 modulator architecture on atm networks, you must prebuffer input data to get a continuous frame rate at the chip input. if high input jitter occurs over an atm without a prebuffer, the whole pll regulation of the input-to-output frame rate fails. you must design the size of the prebuffer according to the maximum jitter expected over the asynchronous transfer mode (atm) network. 2.3 i/o the following subsections describe the input and output of the L64777. 2.3.1 input the qam modulator accepts serial input data at a maximum 54 mhz clock frequency on the iclk pin. in byte-parallel input mode (parallel mode), the maximum frequency on iclk is 10 mhz. dvalidin distinguishes between valid and invalid input data on din[7:0]. errorin marks incorrect packets in the transport header, in case a preceding device passes erroneous information. the input error ?ag is transferred into the transport_error_indicator bit of mpeg transport packets. either the fstartin pulse or the sync_byte detection (0x47 for mpeg transport packets) establishes input synchronization. the fstartin pulse marks the ?rst bit, the most signi?cant bit of an mpeg sync_byte in serial input mode (serial mode), or the sync_byte in parallel mode. the fstartin pulse synchronizes the process of forming bytes from bits in serial mode. if no such synchronization signal is applied, the input synchronizer searches for the programmed sync_byte occurring in the programmed sync length. in parallel mode, the L64777 assumes the byte boundaries are correct and compares the sync_byte in parallel to the incoming bytes. a ?ywheel circuit stabilizes the synchronization to a sync_byte, while synchronization by external pulses feeds directly into the internal control circuits (see section 2.4, input synchronization, page 2-10). 2.3.2 output signals the L64777 outputs the i and q components of its signal on two separate analog output interfaces (see figure 2.4). the output interface contains two internal 10-bit digital-to-analog converters.
i/o 2-7 figure 2.4 analog i/q output interface diagram the differential outputs terminate externally (the external components must provide termination to both differential lines, and the dac achieves maximum linearity in differential mode). the L64777 i and q component outputs are available in 10-bit digital format. the related clock depends on the pll mode: oclk is used in mode 1; pclk is used in mode 2. the output format can be programmed either as a twos complement, or as a sign magnitude representation. the analog i- and q-modulated output signals are at a sampling rate of oclk, which is four times the qam symbol rate. the input to the digital-to-analog conversion is available also in a digital format at the dig_i and dig_q bus pins. avdd1/comp1 vref1 10-bit dac 10 avss2 avdd2/comp2 differential q output differential i output vss avss1 r vddx1 3 on-chip off-chip qam_i, qam_in qam_q, qam_qn q filter output i filter output functional (test mode is selected using vref2 vddx2 10 10-bit dac r 3 2 10 test bus ft mode pins)
2-8 modulator architecture the internal vco of the L64777 can generate oclk, or it can use the oclk input. the L64777 selects oclk based on the selected pll mode. oclk drives the nyquist filter and generates the symbol-processing clock inside the chip after the input circular buffer. the beginning of a sync frame at the i and q output is indicated by the fstartout signal. fstartout lets the L64777 watch for gap insertion in the rs code at the fifo read side. as long as the read pointers are halted to generate gaps, fstartout remains high for the number of rs check words plus one cycle. for example, fstartout is one symbol clock cycle long if no gap is inserted; it is 17 symbol clock cycles long if a gap for 16 rs check words is inserted. the signal firstout indicates the head of a sequence after reset with the sstartin signal. the negative slope of the sstartin input pin controls sequence reset. note: dvalidin must be active for at least one iclk cycle when sstartin is high and when sstartin is low. 2.3.3 control interface an external cpu uses the L64777 serial control interface to control and setup the programmable parameters of the chip. this interface is a slave- type only, connected to the same serial bus as lsi logic l64724. the chip has ?ve hardwired msbs and takes two lsbs directly from the input pins sb_base[1:0]. the addressing scheme in the L64777 complies with that of the lsi logic l64724, but due to its small, seven-bit internal address space, the L64777 supports only group 0 and group 2 registers. it ignores all others. bits [2:0] within the ?rst data byte transmitted to the device specify the group. bit 6, msb bit 5 bit 4 bit 3 bit 2 bit 1 bit 0, lsb 1 1010 sb_base.1 sb_base.0
i/o 2-9 group 0 is the address pointer register (apr); the i 2 c-compatible serial control interface loads the address byte into apr0 (see appendix a, "programming the L64777 in serial host interface mode" ), for programming details. reading or writing from group 2 causes a data transfer with the device address speci?ed by apr0: if apr0 is set to zero, the serial control interface expects a write access with 196 data bytes to load the ?lter coef?cients; it does not apply an autoincrement to apr0. if apr0 is not at zero, the serial control interface expects only a single data byte and applies an autoincrement to the apr0. the detailed timing of the serial bus is given in appendix a. the serial bus runs at a maximum 400 khz clock rate. the serial control interface can transfer reads and writes in single-byte or burst mode. it must access the status registers 12 and 13 with single-byte reads. the division factor for converting oclk down to the symbol clock is always four. input synchronization works at the iclk rate, either on a bit or byte clock. energy dispersal (scrambling), reed-solomon encoding, convolutional interleaving, byte to m-tuple conversion, differential encoding, and qam mapping operate at the symbol clock rate (oclk/4). the ?nal nyquist ?lter works on the oclk rate. incoming bits are provided with an input clock (iclk) and a validation signal (dvalidin), which indicates the rising edges of iclk that are carrying valid data. these inputs feed into a 128-word circular fifo buffer. the output carries a continuous data stream if the pll is properly locked. figure 2.5 required relation of iclk and din/dvalidin input waveforms valid data valid data invalid data invalid data din dvalidin iclk
2-10 modulator architecture 2.3.4 serial microprocessor interface a bidirectional microprocessor interface allows write and con?dence read-back of internal registers. no interaction during operation is required with the microprocessor, but all registers must be con?gured after a reset to guarantee proper operation of the device. a default setup that requires no microprocessor download is built in for 64 qam. in the L64777, the group 2 register 0 acts as a sequential download register that feeds the 196 bytes of ?lter coef?cients. after every write, the user can read back the last written coef?cient to verify the tail entry of the coef?cients shift register. the L64777 uses all other registers nonsequentially; these can be read back directly. 2.4 input synchronization the L64777 transport interface reads the data stream from the transport source, identi?es the position of the synchronization bytes, and strips off invalid data. the transport interface can operate in either parallel or serial mode. the L64777 can synchronize the transport interface in two ways. in both modes, it works synchronously with iclk and reads all signals, including input data, on the raising edge of iclk. in external synchronization mode, the transport interface speci?es the position of the external sync byte by asserting fstartin high during sync byte input. in serial mode, the interface must assert the signal high during the ?rst bit (msb) of the input stream. in internal synchronization mode, the L64777 does not require a block start indication and ?nds the position of the programmed sync byte automatically. the transport interface also can apply the signal dvalidin, indicating valid input data, to allow gaps between input bytes. to avoid cyclic buffer overrun or underrun, the average data input rate, measured over the programmed block length, must not differ from the nominal payload rate of the generated qam signal. the circular buffer inside the L64777 allows a maximum 64-byte compensation of the input stream.
input synchronization 2-11 synchronizing the qam modulator with an input pulse at sstartin sets the byte and block boundaries with this external pulse. the transport interface can reinsert the programmed sync byte at the location de?ned by the external pulse. in both the internal and external modes, the transport interface can program the block length and the value of the sync byte. the block length must be less than 256 bytes. after the L64777 achieves synchronization, it either takes the sync byte from the fifo, or it inserts the sync byte into the modulated stream according to the programmed sync byte. only the latter action eliminates any error in the input sync byte, as long as the modulator remains synchronized (see section 2.6.3, energy dispersal (scrambler) unit for more information). given a bit stream consisting of a sequence of ts packets, the sync stage searches for the preprogrammed sync byte (0x47). upon meeting the sync acquisition criteria, the sync stage issues the control strobes for the downstream modules. in addition to synchronizing the L64777 to sync_bytes contained in the input stream, the L64777 can be forced into synchronization by external sync pulses; the modulator can be made to reinsert the programmed sync_byte at the sync pulse position. the transport interface can either pass on a transport error indicator (tei) unchanged from the input transport stream, or it can force the tei to indicate an error with the errorin signal. the L64777 observes the forced signal during the sync byte input and ignores it for the rest of the input packet. the L64777 input stage can operate either in parallel or serial mode. the device receives parallel input for connection to transport layer multiplexers at low frequency but with 11 input lines (clk, 8 lines data, fstartin, and dvalidin, if required). the L64777 can mark the mpeg frame sync_byte with a pulse on fstartin to identify the beginning of a frame. together with fstartin, the L64777 can insert sync bytes and error-correction information into the 204 byte frames. figure 2.6 shows the fifo clock conversion from the iclk domain to the oclk domain.
2-12 modulator architecture figure 2.6 fifo clock conversion the L64777 synchronizes the input in the iclk domain and transfers it to the oclk domain with a reserved bit in the circular buffer. it uses a second bit to transfer the incoming error ?ag for further insertion into the most signi?cant bit (msb) of the second byte of a sync frame, according to the mpeg-2 standard. the L64777 also synchronizes the sstartin pin through the circular buffer, allowing it to lock the beginning of any long-term sequence to the sync_byte location of the next sync block. if this pin is not activated after a reset, all generated sequences run free. when using the L64777 with the l64724, select parallel mode, which is supported with external synchronization pulses. use the spi of l64724 in mode 2 (204 cycle frames with dvalidin low during the check bytes). a tei bit set in the transport stream indicates frames with errors. a single-line transmission connection to the serial input of the L64777 device generally requires synchronizing on the sync_byte within the 128 words sync detector fstartin serial/parallel sync word block length circular buffer 8 8 error sync scrambler sync err.flg. ser/par convert errorin sync word pointer collision alarm iclk domain oclk domain din[7:0]* sstartin data insync fifo scrambler insert insert word flag * note that din[7:0] is valid data, which is the result of d[7:0] and dvalidin high
input synchronization 2-13 bitstream. if the microprocessor interface selects internal synchronization, the L64777 looks for an 8-bit sync pattern s, repeated in the din[0] input data stream with a given period of p bytes. for an mpeg-2 dvb transmission , s = 0x47 an d p = 204. the values s and p are programmable in the chip to accommodate all applications based on mpeg and mpeg-derived standards. parallel operation requires byte-aligning the sync_byte to achieve data-dependant synchronization. for serial input, the L64777 searches the sync_byte in all possible bit positions and automatically detects the byte-alignment. in the L64777, the sync algorithm is ?xed to a procedure with programmable values of s and p. in order to achieve the required functionality at the lowest possible gate count, you can select from three values of track steps, which are the number of ?ywheel repetitions required to declare the states syncok and loss-of-sync. there are two phases to the sync algorithm procedure: the sync acquisition phase, and the sync tracking phase. 2.4.1 sync acquisition phase in the sync acquisition phase, the number of sync detections required for sync and loss is programmable from 3 to 5. ts is the designation for the number of track steps. after ts error-free consecutive detections of the sync byte s at the correct locations, the L64777 declares synchroniza- tion; if a mismatch occurs, it goes back to the search state. validating the detection of the sync word three times ensures a probability of false alarm equal to p fa =(2 - 8 ) 3 = 6*10 - 8 . validating the detection of the sync word ?ve times insures a probability of false alarm equal to p fa =(2 - 8 ) 5 = 9*10 - 13 . figure 2.7 shows the states occurring in the sync acquisition phase. figure 2.7 sync acquisition phase s0 b0 s1 a0 s2 a a to state s3 b
2-14 modulator architecture the abbreviations in the illustration indicate the following states: s0 is the sync pattern research state. when s is detected, transition a0 leads to state s1. if s is not detected, transition b0 maintains state s0. s1 is a retest state. period (p) bytes after s detection in state s0, the detection of s is retested. if s is detected again, transition a leads to state s2. if s is not detected, transition b leads back to state s0. s2 again tests detection of s after period p. if correct detection occurs, transition a leads to the sync tracking phase. if not, transition b leads back to s0. 2.4.2 sync tracking phase the sync tracking phase checks the detection of s at the correct location (i.e., every p bytes). ts - 1 mismatches are tolerated, but at the last mismatch the L64777 declares a loss-of-sync and goes back to state s0 to look for new synchronization. figure 2.8 shows the states occurring in the sync tracking phase. figure 2.8 sync tracking phase the abbreviations in the illustration indicate the following states: s3 is a synchronized state. if no mismatches occur, transition a maintains this state. if a wrong word is detected at the location where s is expected, transition b leads to state s4. s4 tests the detection of s after an interval of p bytes since the last detection test. if s is detected, transition a leads back to synchronized state s3. if not, transition b leads to s5. s3 a s4 b s5 b a from a state s2 b to state s0 a
input synchronization 2-15 s5 again test the detection of s after period p. if s is detected, transition a leads back to synchronized state s3. if not, transition b leads back to s0 to look for another sync location. to review the transitions in the sync acquisition and sync tracking phases: transition a0 occurs when word s is detected. transition b0 occurs when word s is not detected. transition a occurs when word s is detected exactly p bytes after the last detection test. transition b occurs when word s has not been detected p bytes after the last detection test. this transition activates a declaration of loss-of-sync. the L64777 activates output syncok in state s3, s4, or s5. this allows easy measurement of synchronization conditions from outside and monitoring during normal operation. the microprocessor interface also provides syncok information. at this interface, the L64777 can read the actual status and a glitch trap (which detects any sync losses between two sync status reads). syncok can also generate interrupts, if the syncok interrupt is not masked (see section 4.2.1, register 12, page 4-10). in order to use a subset of the device with random data (without frame structure), bypass the synchronization mechanism by setting the unconstrained bit in the register map (see section 4.1.10, register 11, page 4-9).
2-16 modulator architecture 2.5 fifo clock conversion the L64777 uses a dual-ported ram to implement the circular buffer fifo function. the circular buffer has a write pointer driven by iclk and a read pointer driven by the symbol clock, oclk/4. the device does not prevent collisions of the pointers; rather, the pll-vco follow-up time and proper initial setup of the pointer distance must guarantee this. for fifo initialization, the L64777 loads a user-programmable pointer distance of 0 to 127 cycles (the fifo delay value of register 2 in group 2) into the read address pointer (after each microprocessor delay register access) and sets the write address pointer to zero (see figure 2.9). after this initialization, both pointers run free, and the oclk to iclk frequency relationship determines how the read and write pointers advance. to allow outside watching of the asynchronous pointers, an alarm comparator indicates when both pointers are equal. because both counters are gray code counters (in which changes occur only in one bit) the spikes and glitches of the asynchronous signals are minimized. when specifying the microprocessor download value for the read pointer initialization, you must use gray code. the write pointer also is gray code counter-driven; it initializes to zero when the read counter is loaded. figure 2.9 fifo pointer concept properly programmed delay values in gray code guarantee that the read pointer is directly opposite the write pointer most of the time; this increases system immunity against pll frequency swings, which might occur during the phases of an unstable input signal. smaller distances also can reduce system delay. read pointer circular buffer 128 words write pointer zero
sync/ef reinsertion unit 2-17 the hexidecimal address sequence of the read (underlined) and write pointers is: 00, 01, 03, 02, 06, 07, 05, 04, 0c, 0d, 0f, 0e, 0a, 0b, 09, 08, 18, 19, 1b, 1a, 1e, 1f, 1d, 1c, 14, 15, 17, 16, 12, 13, 11, 10, 30, 31, 33, 32, 36, 37, 35, 34, 3c, 3d, 3f, 3e, 3a, 3b, 39, 38, 28, 29, 2b, 2a, 2e, 2f, 2d, 2c, 24, 25, 27, 26, 22, 23, 21, 20, 60, 61, 63, 62, 66, 67, 65, 64, 6c, 6d, 6f, 6e, 6a, 6b, 69, 68, 78, 79, 7b, 7a, 7e, 7f, 7d, 7c, 74, 75, 77, 76, 72, 73, 71, 70, 50, 51, 53, 52, 56, 57, 55, 54, 5c, 5d, 5f, 5e, 5a, 5b, 59, 58, 48, 49, 4b, 4a, 4e, 4f, 4d, 4c, 44, 45, 47, 46, 42, 43, 41, 40. the L64777 download through the microprocessor interface starts with the beginning read pointer value. the write pointer start value is always ?xed to zero. every time the L64777 accesses the fifo delay value in the microprocessor interface (fdel, see section 4.1.3, register 2, page 4-5), the pointers are reset to the these values. if the L64777 is programmed to the fifo autoreset mode (see section 4.1.7, register 6, page 4-7), it forces the pointers to the value in the fdel register on the read side and to zero on the write side after every fifo collision. attention: the only legal load values for the read pointer are gray code numbers with even parity, which means an even number of 1s (underlined in the above table). therefore, the fifo delay increment can only be in steps of two. the device achieves maximum delay with a value of 0x41; the optimum (center) distance to overrun and underruns is 0x60. 2.6 sync/ef reinsertion unit the following subsections describe the sync/ef modes, error ?ag insertion, and scrambler.
2-18 modulator architecture 2.6.1 sync insertion mode the sync/ef unit inserts new sync words if that mode is programmed (see section 4.1.2, register 1, page 4-4). sync insertion can be useful to work against bit errors in sync bytes, even if sync is already inserted in the stream. if the bitstream contains sync bytes that the device uses for synchronization, the regenerated sync bytes conceal single errors in the synchronization pattern. in unsynchronized states s0, s1, and s2, the L64777 bypasses data bits without any modi?cation of the sync byte. after it establishes synchronization (in states s3, s4 and s5), the device inserts the regenerated sync pattern based on the programming of register 1. 2.6.2 error flag insertion the next processing task is the error ?ag handling for mpeg-2 transport packets. if errorin indicates a decoder error at the ?rst byte of a frame, the L64777 sets the transport_error_indicator bit of the mpeg-2 packet. this is the msb of the second byte in a packet (see figure 2.10). if there is no error indication, the L64777 passes the transport_error_indicator bit transparently. figure 2.10 transport error flag insertion 2.6.3 energy dispersal (scrambler) unit the function of the scrambler is speci?ed for the serial domain by the digital broadcasting systems for television sound and data services: framing structure, channel coding and modulation cable systems . the energy dispersal module (scrambler) operates in parallel mode based on the algorithm of the serial domain. figure 2.11 illustrates the basic serial architecture of the scrambler. din[0] fstartin errorin start of transport packet sync_byte (0x47) 0 71 2 3 4 5 6 ...dont care on /error...
sync/ef reinsertion unit 2-19 figure 2.11 scrambler basic serial architecture the scrambler block consists of two major modules: one to generate a pseudo-random binary sequence (prbs) that modi?es the incoming data stream, and the other a control module that properly aligns data with the prbs. the prbs the descrambler module produces is characterized by the following generator polynomial: for initialization, choose a speci?c value for the 15-tap shift register (see figure 2.12). figure 2.12 shift register initialization sequence the L64777 uses a special sync word (0xb8), generated by inverting every eighth transport sync word (0x47), to align the descrambler with the incoming data stream. the L64777 applies the ?rst bit of the prbs to the ?rst data bit following the inverted sync byte and freezes the scrambler register contents during gaps for rs check words. during the following noninverted sync words, the descrambler sequence generator is kept in operation but does not modify the data stream. the L64777 resets the descrambler sequence after every inverted sync word. the scrambled bitstream 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 shift register bitstream xor xor shift_enable initial load & control 1 x 14 x 15 ++ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0
2-20 modulator architecture sstartin input signal can preset the phase of the inverted sync_byte and the whole scrambler sequence. the microprocessor can switch off the scrambler module through register 3 (see section 4.1.4, register 3, page 4-5). the selected microprocessor control applies the sequence of start, run, and disable modes, depending on the programmed sync block length values in register 4 (see page 4-6). 2.7 reed-solomon encoder reed-solomon (rs) error correction codes are systematic and operate on bytes rather than single-bit data streams. the codes are expressed by convention as two numbers, the ?rst indicating the total code word length (n), and the second indicating the number of message bytes (k). the difference between these two numbers (n - k) is the number of check bytes. dvb uses this generator polynomial for rs codes: where r = 16 (checkbytes), and a is a root of the binary primitive polynomial: a data byte (d 7 ,d 6 ,...d 1 ,d 0 ) is identi?ed with the element d 7 a 7 +d 6 a 6 +...+ d 1 a +d 0 in gf (256), the ?nite ?eld with 256 elements. the error-correcting power of an rs code is related to the number of redundant check symbols in its code words. in general, an rs code with 2t check symbols per code word can correct up to t byte errors per code word. higher redundancy allows more errors to be corrected. ecc devices have a speci?c lexicon associated with their ability to correct transmission messages; the terms used for variables in the reed-solomon core are as follows: x a i + () i0 = r1 C ? x 8 x 4 x 3 x 2 1 ++++
reed-solomon encoder 2-21 r check bytes the encoder generates and appends check bytes to the incoming message according to the reed-solomon error-correction encoding. the decoder uses check bytes to locate and correct errors due to transmission. d detection power detection power has a minimum value of and a maximum value of r. k message length the message is comprised of multiple bytes. the size of the message varies depending on the code word length and the check bytes used, where k = n - r. m symbol size the symbol size m is 8 bits ?xed. n code word length this is the sum of the number of message bytes and the number of check bytes (k + r). t number of error corrections this variable is the maximum number of error corrections performed by the decoder. its maximum value is: 2.7.1 forward error correction (fec) fec requires an encoder that appends redundant check information to the message before transmission. the bytes with an indeterminate number of bits are referred to as symbols. the message symbols and following redundant check symbols make up code words. the check symbols are redundant because they are derived from the message and are appended to the message. check symbols are also referred to as redundant check bytes, and sometimes as correction bytes. figure 2.13 illustrates a code word. figure 2.13 code word structure r 2 ---- r 2 ---- n code word bytes k message bytes r redundant check bytes
2-22 modulator architecture a code word is a block of n bytes that includes k message symbols and n - k check bytes (r). the check bytes, or symbols, are some fraction of the message symbols. a large number of check symbols allows the decoder to correct a large number of transmission errors. the redundant check symbols in a message allow a decoder at the receiving end of a transmission line to detect transmission errors and reconstruct the original message content. figure 2.14 shows a block diagram of the basic encoder and decoder functions in a transmission system. figure 2.14 forward error correction data path after generating a code word, the encoder transmits it to a decoder. the decoder compares the bitstream in the message data to the encoding in the check bytes to detect transmission errors. the L64777 can reconstruct the original message precisely from the check symbols, as long as the code word has no more than byte errors, where r = the number of redundant check bytes. 2.7.2 error handling and correction a bit error occurs when a transmitted 0 is received as a 1, or vice versa. a byte error occurs when one or more bits in the byte have errors. for example, a byte with only one bit error is counted as one byte error, and a byte with m bit errors (all bits are inverted) is also counted as 1 byte error. as long as a code word has no more than t = byte errors, the rs decoder corrects all errors. to achieve rs encoding at the lowest possible gate count and power consumption, the check byte parameters of the rs encoder in the L64777 are ?xed to r = 16, according to the dvb standard. when the rs encoder is switched off, data feeds through without check-word insertion at an internal delay of two clock cycles. encoder decoder corrected channel message data message data message + check bytes = code word code word - check bytes = message r () 2 r () 2
convolutional interleaver 2-23 2.8 convolutional interleaver figure 2.15 is a block diagram of a convolutional interleaver system, which rearranges the ordering of a sequence of symbols in a deterministic manner. a (b, n) periodic interleaver has the following characteristics: the minimum separation at the interleaver output is b symbols for any two symbols that are separated by less than n symbols at the interleaver input. any burst of b < b errors inserted by the channel results in single errors at the deinterleaver output. the scheme is also referred to as a convolutional interleaver/ deinterleaver (based on the forney approach). figure 2.15 interleaver block diagram the L64777 interleaver performs periodic interleaving with two ?xed parameters: b, the desired interleaving depth, and m, de?ned as: the values of the interleaver in the L64777 are: n = 204, b = 12, and m = 17. you can switch off the interleaver. it is fully transparent with an intrinsic delay of three clock cycles. the main modules are a set of con?gured ram-based delay lines to implement the proper delay for individual data bytes, and a controller to handle and generate the strobes needed by subsequent modules in the data path. 2m (b - 1)m encoder channel decoder t m 2m (b - 1)m t m m n b --- - =
2-24 modulator architecture the interleaver must recover the block boundaries, and the sstartin pin indicates them by internal strobes; it also resets the interleaver sequence. you can program the interleaver so that all data fed into the interleaver ram before the very ?rst arrival of a sstartin negative slope is set to zero. this eases operation veri?cation and debugging during development when the interleaver ram is completely initialized with zero values. you must apply a fresh reset to feed zeros after an active sstartin slope. the interleaver and the deinterleaver, in sequence, output the original byte stream after a delay of in the L64777, the delay = (11 x 12 x 17) = 2244 clock cycles. thus, the delay from the time of the ?rst input byte to the ?rst valid output byte in the maximum delay path of the interleaver is half of this value, which is 1122 valid clock cycles. if the qam is not in 256 mode, the interleaver inserts invalid cycles in an eight-byte sequence, which proportionally increases the delay time. the zero delay path in the interleaver delivers data with a propagation delay of three clock cycles. this is equal to the delay of the interleaver when it is off. 2.9 bytes to m-tuples converter this unit cuts down bytes to slices of m = 1, 2, 3, 4, 5, 6, 7, and 8 bits. the programming parameter, msize (see section 4.1.2, register 1, page 4-4), must be set to m - 1. the order is the msb of the oldest byte ?rst. see the digital broadcasting systems for television sound and data services: framing structure, channel coding and modulation cable systems for a detailed speci?cation. when cutting six-bit symbols, it cuts three bytes into four symbols. the case of four-bit symbols is trivial (eight bits are split into two sets of four bits each). figure 2.16 outlines the basic principle for symbol cutting out of bytes. modes for m = 5 and m = 7 are similar. delay b 1 C () bm =
bytes to m-tuples converter 2-25 figure 2.16 symbol cutting from bytes the general control unit feeds packets of eight bytes and a valid indicator to the convertor. thus, the conversion is as shown in figure 2.17. figure 2.17 byte to symbol conversion b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 byte n byte n + 1 byte n + 2 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b5 b4 b3 b2 b1 b0 symbol t symbol t symbol t + 1 symbol t + 1 symbol t + 2 symbol t + 3 symbol t + 2 symbol t + 3 symbol t + 4 symbol t + 5 b5 b4 b3 b2 b1 b0 b5 b4 b3 b2 b1 b0 b5 b4 b3 b2 b1 b0 m = 8 m = 4 m = 6 time byte 4 byte 0 byte 1 byte 2 byte 3 m = 5 bit 4 bit 0 bit 1 bit 2 bit 3 byte 0 byte 1 byte 2 byte 3 m = 4 bit 0 bit 1 bit 2 bit 3 byte 4 byte 0 byte 1 byte 2 byte 3 m = 7 bit 4 bit 0 bit 1 bit 2 bit 3 byte 4 byte 0 byte 1 byte 2 byte 3 m = 6 bit 4 bit 0 bit 1 bit 2 bit 3 time byte 4 byte 0 byte 1 byte 2 byte 3 m = 8 bit 4 bit 0 bit 1 bit 2 bit 3 bit 5 bit 6 bit 7 byte 5 byte 6 byte 7 bit 5 bit 6 byte 5 byte 6 byte 5 bit 5 byte-to-symbol conversion
2-26 modulator architecture 2.10 differential encoder and qam mapping this block performs differential encoding and mapping for 16 and 64 qam, as speci?ed in the digital broadcasting systems for television sound and data services: framing structure, channel coding and modulation cable systems , the baseline document, and its extensions. the qam 256 mapping is taken from the dvb document 1190. the encoder performs differential encoding on the two most signi?cant bits of each symbol, as shown in the block diagram in figure 2.18 and speci?ed in equations 2.1 and 2.2. figure 2.18 differential encoder and qam mapping to clarify the underlying concepts in figure 2.18, here are two examples: 1. ifm=4,a k is bit 3, b k is bit 2, and the lsb = (m - 2) bits = bits [1:0]. 2. ifm=6,a k is bit 5, b k is bit 4, and the lsb = (m - 2) bits = bits [3:0]. equation 2.1 equation 2.2 mapping performs a table look-up for the concatenation of the (m - 2) least signi?cant bits of each symbol with the differentially generated bits i k and q k . in 64 qam mode, the mapping block of the differential encoder maps the 6-tuples to two 3-bit values for i and q output. in 16 qam mode, it maps the 4-tuples to two 2-bit values. for lower qam modes, it aligns the i and q output values to the msb and stuffs the least-signi?cant bit (lsb) with ones. 8 byte to differential encoder mapping msb = a k b k i k q k i[3:0] q[3:0] m-tuple from interleaver msb - 1 lsb m - 2 i k a k b k ? () ? () a k i k 1 C ? () a k b k ? () a k q k 1 C ? () + = q k a k b k ? () ? () b k q k 1 C ? () a k b k ? () b k i k 1 C ? () + =
square root nyquist filter 2-27 differential encoding has an in?nite error propagation. you can switch it off independently from the mapping function (see bit 3 of register 6, on page 4-8). 2.11 square root nyquist filter this pulse-shaper module implements a programmable square-root raised cosine ?ltering function with a default 15% roll-off factor. the precision of the internal nyquist ?lter computations, and the width of the output data bus, are suf?cient for qam modulations up to 256. the ?lter operates at four times the oversampling rate. figure 2.19 illustrates the structure of the pulse shaper. figure 2.19 pulse shaper structure note that the 20 bits per channel is a result of the length of each coef?cient register (2 11 ) plus the length of inq (2 4 ) plus the number of stages (30 = 2 5 ). the total number of coef?cients is 124 (there is one coef?cient set for each of the four phases multiplied by the mac structure, which contains 31 multipliers). each of the two i and q branches has one ?lter, realized as polyphase structures. each ?lter consists of four ?lter branches, which compute 1-phase ?lter results at the symbol rate. thus, the L64777 nyquist ?lter module generates the desired pulse shape by combining the outputs of four identical ?lter branches for i and q. from coef?cient register (register 0) to shifter numbers represent coef?cient word width of mac structures is[19:0], 11 bit qs[19:0] c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c23 c24 c25 c26 c27 c28 c29 c30 offset 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 the big adder
2-28 modulator architecture for an oversampling factor of four, the ?lter executes the above sequence at four times the symbol rate (60 mhz in pll mode). each multiply accumulator (mac)-structure contains 31 multipliers whose outputs add up to the desired result. the pulse shaper module connects one input of each multiplier to a delayed version of the ?lter input data; the other multiplier input is connected to one of four coef?cient registers through a multiplexer. the pulse shaper clocks the delay line for idata and qdata with the symbol clock rate. the coef?cient and multiplier width are as described below. the pulse shaper interprets all data as twos complement. each mac- structure contains an additional input to the adder array to allow for the addition of an 11-bit value to compensate for an offset. the pulse shaper treats these offset coef?cients like regular coef?cients, except that it adds them directly to the mac outputs. there is one offset coef?cient for each phase. the shifter block adjusts the internally generated ?lter result to accommodate the limited range of the internal d/a-converter. the standard mapping after reset is a ?ve-bit shift to the right, which means is[5] to i[0], is[6] to i[1] and so on. the shifter treats the q-branch accordingly. by applying a value different from zero to the bits_to_shift[3:0] input of the shifter (using register 0), the shifter connects is to i, and qs to q, so that the lowest bits of is and qs are truncated, while the more signi?cant bits are hooked to the i and q outputs. the bits_to_shift input can assume a maximum value of 15, thus mapping is[15] to i[0], is[16] to i[1], and so on. the ?lter output value is not limited to maximum positive or negative values before shifting, so it is the users responsibility to download coef?cients and an appropriate shifting value to avoid output over?ow and under?ow. figure 2.20 illustrates the output scaling by an arithmetic shift to the right.
square root nyquist filter 2-29 figure 2.20 output scaling by arithmetic shift right the shifter treats the value of bits_to_shift[3:0] like a coef?cient, and the value is available separately for every phase. this means that the hardware of the ?lter is multiplexed in such a way that there are the same coef?cient registers for the i and q channel, and each of the two macs switches between four banks of coef?cients cyclically, driven by oclk. setting all coef?cients to zero (except the center coef?cient, which is 1), offers a bypass mode for the ?lter. the interpolator following the nyquist ?lter receives 12-bit resolution in pll mode 2. program the shifter accordingly to make the increase precision available to the interpolator; for example: to 3 rather than 5. 2.11.1 filter setup procedure the ?lter module is loaded with 31 ?lter coef?cients sequentially, with four blocks of 49 bytes in the phase_0, phase_1, phase_2, and phase_3 registers (register 0 of group 2). the same data controls the i and q data path in parallel. also, the ?lter is loaded with four bits_to_shift and an 11-bit offset value for each phase. it is speci?ed within 49 bytes in each phase, as shown in table 2.1. the complete setup sequence consists of 4 * 49 = 196 bytes for all four phases. the ?lter organizes the coef?cient registers for each register bank as described below, using the coef?cient enumeration shown in the block diagram. note that no meaningful operation can be performed while the ?lter is being programmed, since the old coef?cients are being shifted out while the new ones are programmed in. shifter i[9:0] shifter q[9:0] bits_to_shift[3:0] is[19:0] qs[19:0]
2-30 modulator architecture as shown in figure 2.18, the ?lter shifts four coef?cient register banks (register 0) sequentially, starting with register 48 and proceeding down to 0. in this con?guration, it shifts bank 3 ?rst, then 49 bytes of bank 2, bank 1, and, ?nally, bank 0. table 2.1 shows the exact allocation of bits within each bank. 2.11.2 example assuming all ?lter con?guration bits are located in a host microprocessor rom array of bytes addressed with [0 to 195], the ?lter coef?cients place phase 0 coef?cients in registers [0 to 48], phase 1 in [49 to 97], phase 2 in [98 to 146], and phase 3 in [147 to 195]. to download this array, the microprocessor must write bytes [195 down to 0] sequentially into address 0 register, highest array address ?rst. after 196 write cycles, the four coef?cient register banks are completely con?gured. during con?guration, the ?lter is not operational to save gates by avoiding double buffering of the coef?cient registers. for different qam modes, the ?lter must load the appropriate sets of coef?cients and shifter values. the default set of coef?cients is a square-root raised cosine ?lter. the ?lter sets the coef?cients in table 2.2 after reset, and it can overwrite them with external programming through the i 2 c-compatible interface. table 2.1 allocation of coef?cient-bits for phase 0 b7 b6 b5 b4 b3 b2 b1 b0 reg # c0.7 c0.6 c0.5 c0.4 c0.3 c0.2 c0.1 c0.0 0 c1.7 c1.6 c1.5 c1.4 c1.3 c1.2 c1.1 c1.0 1 C c0.10 c0.9 c0.8 C c1.10 c1.9 c1.8 2 c2.7 c2.6 c2.5 c2.4 c2.3 c2.2 c2.1 c2.0 3 c3.7 c3.6 c3.5 c3.4 c3.3 c3.2 c3.1 c3.0 4 C c2.10 c2.9 c2.8 C c3.10 c3.9 c3.8 5 c4.7 c4.6 c4.5 c4.4 c4.3 c4.2 c4.1 c4.0 6 c5.7 c5.6 c5.5 c5.4 c5.3 c5.2 c5.1 c5.0 7 C c4.10 c4.9 c4.8 C c5.10 c5.9 c5.8 8
square root nyquist filter 2-31 c6.7 c6.6 c6.5 c6.4 c6.3 c6.2 c6.1 c6.0 9 c7.7 c7.6 c7.5 c7.4 c7.3 c7.2 c7.1 c7.0 10 C c6.10 c6.9 c6.8 C c7.10 c7.9 c7.8 11 c8.7 c8.6 c8.5 c8.4 c8.3 c8.2 c8.1 c8.0 12 c9.7 c9.6 c9.5 c9.4 c9.3 c9.2 c9.1 c9.0 13 C c8.10 c8.9 c8.8 C c9.10 c9.9 c9.8 14 c10.7 c10.6 c10.5 c10.4 c10.3 c10.2 c10.1 c10.0 15 c11.7 c11.6 c11.5 c11.4 c11.3 c11.2 c11.1 c11.0 16 C c10.10 c10.9 c10.8 C c11.10 c11.9 c11.8 17 c12.7 c12.6 c12.5 c12.4 c12.3 c12.2 c12.1 c12.0 18 c13.7 c13.6 c13.5 c13.4 c13.3 c13.2 c13.1 c13.0 19 C c12.10 c12.9 c12.8 C c13.10 c13.9 c13.8 20 c14.7 c14.6 c14.5 c14.4 c14.3 c14.2 c14.1 c14.0 21 c15.7 c15.6 c15.5 c15.4 c15.3 c15.2 c15.1 c15.0 22 C c14.10 c14.9 c14.8 C c15.10 c15.9 c15.8 23 c16.7 c16.6 c16.5 c16.4 c16.3 c16.2 c16.1 c16.0 24 c17.7 c17.6 c17.5 c17.4 c17.3 c17.2 c17.1 c17.0 25 C c16.10 c16.9 c16.8 C c17.10 c17.9 c17.8 26 c18.7 c18.6 c18.5 c18.4 c18.3 c18.2 c18.1 c18.0 27 c19.7 c19.6 c19.5 c19.4 c19.3 c19.2 c19.1 c19.0 28 C c18.10 c18.9 c18.8 C c19.10 c19.9 c19.8 29 c20.7 c20.6 c20.5 c20.4 c20.3 c20.2 c20.1 c20.0 30 c21.7 c21.6 c21.5 c21.4 c21.3 c21.2 c21.1 c21.0 31 C c20.10 c20.9 c20.8 C c21.10 c21.9 c21.8 32 c22.7 c22.6 c22.5 c22.4 c22.3 c22.2 c22.1 c22.0 33 table 2.1 allocation of coef?cient-bits for phase 0 (cont.) b7 b6 b5 b4 b3 b2 b1 b0 reg #
2-32 modulator architecture c23.7 c23.6 c23.5 c23.4 c23.3 c23.2 c23.1 c23.0 34 C c22.10 c22.9 c22.8 C c23.10 c23.9 c23.8 35 c24.7 c24.6 c24.5 c24.4 c24.3 c24.2 c24.1 c24.0 36 c25.7 c25.6 c25.5 c25.4 c25.3 c25.2 c251 c25.0 37 C c24.10 c24.9 c24.8 C c25.10 c25.9 c25.8 38 c26.7 c26.6 c26.5 c26.4 c26.3 c26.2 c26.1 c26.0 39 c27.7 c27.6 c27.5 c27.4 c27.3 c27.2 c271 c27.0 40 C c26.10 c26.9 c26.8 C c27.10 c27.9 c27.8 41 c28.7 c28.6 c28.5 c28.4 c28.3 c28.2 c28.1 c28.0 42 c29.7 c29.6 c29.5 c29.4 c29.3 c29.2 c29.1 c29.0 43 C c28.10 c28.9 c28.8 C c29.10 c29.9 c29.8 44 c30.7 c30.6 c30.5 c30.4 c30.3 c30.2 c30.1 c30.0 45 offset.7 offset.6 offset.5 offset.4 offset.3 offset.2 offset.1 offset.0 46 C c30.10 c30.9 c30.8 C offset.10 offset.9 offset.8 47 CCCC shift.3 shift.2 shift.1 shift.0 48 table 2.2 default nyquist filter coef?cients tap phase0 phase1 phase2 phase3 #00000 #1 0 - 1 - 10 #20000 #30111 #4 - 1 - 3 - 3 - 1 #53551 #6 - 4 - 9 - 7 - 1 table 2.1 allocation of coef?cient-bits for phase 0 (cont.) b7 b6 b5 b4 b3 b2 b1 b0 reg #
square root nyquist filter 2-33 #7 8 13 10 - 1 #8 - 14 - 19 - 13 3 #9 20 28 16 - 8 #10 - 31 - 38 - 20 15 #11 46 51 23 - 27 #12 - 69 - 71 - 26 48 #13 107 105 28 - 95 #14 - 191 - 184 - 29 257 #15 593 862 965 862 #16 593 257 - 29 - 184 #17 - 191 - 95 28 105 #18 107 48 - 26 - 71 #19 - 69 - 27 23 51 #20 46 15 - 20 - 38 #21 - 31 - 81628 #22 20 3 - 13 - 19 #23 - 14 - 11013 #24 8 - 1 - 7 - 9 #25 - 4155 #26 3 - 1 - 3 - 3 #27 - 1111 #280000 #29 0 0 - 1 - 1 #300000 table 2.2 default nyquist filter coef?cients (cont.) tap phase0 phase1 phase2 phase3
2-34 modulator architecture the default offset value for all four phases is 0. to shift the shifter by default, set it to 5 bits. 2.11.3 default filter characteristics figure 2.20 shows the characteristics of the L64777 default ?lter. figure 2.21 square-root raised cosine filter 2.12 global control and pll module the L64777 interface supports serial and parallel input modes at the input interface. the global control generates the clocking for the input and output interfaces; it also controls the data path. it contains all the necessary logic to chain the processing units together. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -8000 -6000 -4000 -2000 0 normalized frequency (nyquist == 1) phase (degrees) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -150 -100 -50 0 50 normalized frequency (nyquist == 1) magnitude response (db) magnitude response (db) 50 0 - 50 - 100 - 150 phase (degrees) 0 - 2000 - 4000 - 6000 - 8000 0 0.9 1.0 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 normalized frequency (nyquist = 1) 0 0.9 1.0 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 normalized frequency (nyquist = 1)
global control and pll module 2-35 the global control manages the output data stream so that it is continuous (no gaps between the symbols), assuming that the incoming data rate is constant (on average). to achieve this, a pll must derive the output clock oclk from the input transport stream rate. the pll module consists of two independent clock dividers for iclk and oclk. the dividers are 15-bit binary counters that have a count sequence length that is programmable through registers 7 through 10. the default values written by the external microprocessor are: oclk divider = 32, iclk divider = 6 for 64 qam. 2.12.1 numerically controlled oscillator (nco) in pll mode 2, an nco generates the internal clocking (oclk, sclk) and the control information for the interpolator. the nco is locked to iclk clock and operates with the processing clock pclk provided from l64724. pclk must be at least twice as fast as the necessary oclk. to lock the loop with low jitter, program the nco with a frequency close to the ideal value obtained from the formulae given for the other pll modes. a phase loop in a second step does the ?ne regulation (see figure 2.22). to ?nd the required initial frequency, the device supports two modes: a frequency measurement unit, and an automated frequency acquisition. these are described in the following sections.
2-36 modulator architecture figure 2.22 nco loop diagram 2.12.2 acquisition phase using the frequency measurement unit during the acquisition phase, the nco bases the measurement on the assumption that the byte clock on the iclk input has a duration of either of n - 1, n, or n + 1 pclk cycles and that the input stays within these bounds for the duration of the measurement. you can program the duration in multiples of 256-byte clock cycles in the ref_dur register (see section 4.2.7, registers 21 and 22, page 4-14). the nco control register (see section 4.2.3, register 14, page 4-12) can control the start of the measurement, and the measurement done bit in register 13 indicates successful completion. if bit 2 of register 14 enables an interrupt, the measurement generates it. after completion of the measurement, the host reads the number of byte clock cycles found with the appropriate length of n ,n+1andn - 1 (from nm_count, n_count, np_countsee sections 4.2.10 through 4.2.12), as well as the value of n (from n_pclksee section 4.2.9). frequency 58 cnt_i cnt_o nco phase_gain exor step oclk interpolator enable_phase_loop = 1 byte clock if serial virtual fifo for automatic npclk, n_count, np_count, iclk threshold step correctio n frequency acquisition phase loop divider divider (for frequency selection) ctrl measurement unit nm_count
global control and pll module 2-37 the host computes the following formulae to get the initial step for phase 2, where ? indicates the average n value. equation 2.3 and from this: equation 2.4 in the above formulae: c1 is the reading from nm_count register. c2 is the reading from n_count register. c3 is the reading from np_count register. n is the reading from n_pclk register. sync length is the number of iclk cycles between sync bytes (for example, 204). valid bytes are the number of valid bytes during the sync interval (for example, 188). ld(qammode) is the number of bits per qam symbol. if the rs encoder is enabled in dvb mode and the spi interface of l64724 is programmed to mode 2, the factor of sync length by valid bytes becomes one. in order to get an accurate initial step, the measurement must run for a long duration. a recommended duration is 250 ms. in general the oclk frequency is calculated as . above, 0 < step <2 23 - 1. start measurement by toggling the start measurement bit (bit 6) in the nco control register 14. if the nco control register is enabled for interrupt (through bit 2 of register 14), an interrupt indicates completion. n ? c 1 n 1 C () c 2 n () c 3 n 1 + () ++ () c 1 c 2 c 3 ++ () --------------------------------------------------------------------------------------- = initial step 2 24 n ? -------- 32 ld qammode () ----------------------------------------- sync length valid bytes ------------------------------ - = f oclk f pclk step 2 24 ------------ =
2-38 modulator architecture 2.12.3 autoacquisition mode to ease the usage of phase 1, the nco can use an automatic frequency acquisition. enable regulation of the nco_loop_enable (bit 5) and set the auto_acqui bit (bit 3) in the nco control register. figure 2.23 outlines the parameter usage during automatic frequency acquisition. figure 2.23 frequency acquisition loop overview init step = init step (reg 16 to 18) measurement duration = ref dur (registers 21, 22) threshold = reg 43 reset virtual fifo step = step + virtual fifo * nco_gain wait until measurement duration has elapsed reset virtual fifo abs(virt fifo) threshold = threshold/2 (register 43) nco_gain = nco_gain/2 + 1 (registers 19, 20) nco_gain > 1 measurement duration = auto_acqui_running = 0 false true below_thres = 0 below_thres = 1 step update indication in reg 13 will be set and reset upon read of the register threshold runs if enable_nco_loop is 1 (register 14) runs if auto_acqui is 1 2 * measurement duration (register 13, bit 5 = 1) (registers 38 and 39) (registers 21 and 22)
interpolator 2-39 note that the virtual fifo, which indicates the fifo under- or over-run, is an internal location. if the nco_gain has reached the smallest possible value of 1, the auto_acquisition terminates. the auto_acqui_running bit (register 13, bit 3) sets to zero, indicating termination. if enabled, the nco can issue an interrupt on this condition. this procedure updates the nco step until the contents of the virtual fifo is zero during the measurement duration. if enable_nco_loop and auto_acqui are not set, it is also possible to set all parameters of the nco loop through the microprocessor interface and to run a frequency acquisition fully controlled by the microprocessor. for monitoring purposes, it is possible to read the current step and nco_gain using the microprocessor interface. 2.12.4 regulation phase when the enable_phase_loop bit is set in the nco control register (register 14, bit 1), the loop starts running a phase compare between the divided reference and the divided feedback clock. the nco must set counters cnt_i and cnt_o according to the rules applied for the other pll modes in registers 7 through 10. the phase loop has a relatively small gain, which can be adjusted in address 42. the nco achieves a phase lock only if the initial frequency is already close to the desired range. 2.13 interpolator in pll mode 2, the interpolator retimes the output samples that the nyquist ?lter calculated. the interpolator is clocked with pclk and generates the output samples in the pclk sampling grid. the interpolator takes the required retiming information from the nco. pclk is at least twice the frequency of the original oclk obtained by the formula for pll mode 1. the square-root raised cosine ?lter also compensates for the sin(x)/x frequency characteristic of the digital-to- analog converter with the faster sampling grid.
2-40 modulator architecture another consideration is that the interpolator receives a 12-bit input from the nyquist ?lter. set the shifter in the nyquist ?lter accordingly (for example: 2). for pll mode 2, the shifter value (which is de?ned in the ?lter coef?cients in register 0 of group 2) is 3; for mode 1, the shifter value is 5. 2.14 serial microprocessor interface the external microprocessor controls the qam modes of operation, 16 to 256 qam. it also controls the mode of input synchronization, that is, whether to lock synchronization to sync bytes or input pulses. the microprocessor interface downloads the ?lter coef?cients and the delay value for proper fifo initialization. the microprocessor interface uses an i 2 c-compatible serial control protocol. the signal behavior is described in appendix a. the interface is slave-only and can not be a master to the serial bus. the base address of the component is composed of a ?xed ?ve-bit address and two selectable bits, which are fed through sb_base[1:0] (see figure 2.24). application of these bits must be on a static basis to ensure proper operation. figure 2.24 serial bus base address the L64777 output pins and microprocessor interface provide error indications (for example, the fifo alarm signal). the following interface signals are used: scl serial control line sda serial data access int_n interrupt, open drain output the same type of two-wire serial interface is available on the lsi logic l64724. bit 6, msb bit 5 bit 4 bit 3 bit 2 bit 1 bit 0, lsb 11010xx
test unit 2-41 attention: the internal microprocessor registers are not double- buffered, and they in?uence the processing modes of the L64777 asynchronously during operation. thus, all mode changes place the chip in an unde?ned state until an sstartin pulse synchronously resets the sequences of the data path. when a firstout pulse grants the sequence reset at the output, the chip becomes fully operational again. the normal chip initialization procedure is as follows: C reset after power-up. C initialize all microprocessor registers. C apply a negative slope of sstartin to reset all sequences at the beginning of the next sync block. C apply a negative slope of sstartin after all mode changes from the microprocessor interface and wait for firstout. also, the serial interface requires a clock for internal operation, either through the oclk input or from the internal vco to program the device. furthermore, there is a lower limit for this clock: its frequency must be at least eight times that of scl. 2.15 test unit the L64777 supports: full scan test bist for the two rams jtag boundary scan digital-to-analog conversion test pll tests select the L64777 test modes through the ftmode pins. the default values for normal operation are: ftmode = 000, scan_enable = 0, tnn = 1. if tnn is cleared, all outputs are high-impedance.
2-42 modulator architecture to guarantee the proper operation of the L64777 in the printed circuit board environment, an additional ieee 1149.1 jtag module is included in the device, which operates on the following pins: trstn = 0 tck = 0 tms = 0 tdi = 0 tdo (output) special test modes are applicable for further functional testing, and the test of the digital-to-analog converters.
L64777 dvb qam modulator technical manual 3-1 chapter 3 interfaces the following chapter describes the interfaces of the chip and the interface operation modes. it consists of the following sections: section 3.1, transport interface, page 3-1 section 3.2, serial control interface, page 3-2 section 3.3, analog output interface, page 3-3 section 3.4, digital output interface, page 3-6 3.1 transport interface the task of the transport interface is to read the data stream from the transport source, to identify the position of the synchronization bytes, and to strip off invalid data. the transport interface can operate in either parallel or serial mode. 3.1.1 synchronization the L64777 can synchronize the transport interface in two ways. in both modes, it works synchronously with iclk and reads all signals, including input data, on the raising edge of iclk. in external synchronization mode, the transport interface speci?es the position of the external sync byte by asserting fstartin to high during the synch byte input. in serial mode, the interface must assert the signal high during the ?rst bit (msb) of the input stream. in internal synchronization mode, the L64777 does not require a block start indication and ?nds the position of the programmed sync byte automatically.
3-2 interfaces 3.1.2 synchronization methods the transport interface also can apply the signal dvalidin, indicating valid input data, to allow gaps between input bytes. to avoid cyclic buffer overrun or underrun, the average data input rate, measured over the programmed block length, must not differ from the nominal payload rate of the generated qam signal. the circular buffer inside the L64777 allows a maximum 64-byte compensation of the input stream. synchronizing the qam modulator with an input pulse at sstartin sets the byte and block boundaries with this external pulse. the transport interface can reinsert the programmed sync byte at the location de?ned by the external pulse. in both the internal and external modes, the transport interface can program the block length and the value of the sync byte. the block length must be less than 256 bytes. after the L64777 achieves synchronization, it inserts the sync byte into the modulated stream according to the programmed sync byte. this has the advantage of eliminating any error in the input sync byte as long as the modulator remains synchronized. 3.1.3 transport error indicator handling the transport interface can either pass on a transport error indicator (tei) unchanged from the input transport stream, or it can force the tei to indicate an error with the errorin signal. the L64777 observes the forced signal during the sync byte input and ignores it for the rest of the input packet. 3.2 serial control interface the L64777 uses a serial control interface to control and setup the programmable parameters of the chip. this interface is a slave-type only, connected to the same serial bus as the lsi logic l64724.
analog output interface 3-3 the chip has ?ve hardwired msbs and takes two lsbs directly from the input pins sb_base[1:0]. the addressing scheme in the L64777 complies with that of the lsi logic l64724, but, due to its small 7-bit internal address space, the L64777 supports only group 0 and group 2. the bit location [2:0] within the ?rst data byte transmitted to the device speci?es the group. group 0 is the address pointer register (apr); the serial control interface loads the following data byte to apr0. reading or writing from group 2 causes a data transfer with the device address speci?ed by apr0: if apr0 is set to zero, the serial control interface expects a write access with 196 data bytes to load the ?lter coef?cients; it does not apply an autoincrement to apr0. if apr0 is not at zero, the serial control interface expects only a single data byte and applies an autoincrement to the apr0. the L64777 ignores group 1 and groups 3 to 7. it does not apply any reading or writing from them. the detailed timing of the serial bus is given in appendix a. the serial bus is designed to run at a maximum 400 khz clock rate. the serial control interface can transfer reads and writes in single-byte or burst mode. it must do read access to the status registers 12 and 13 as a single-byte read. 3.3 analog output interface the L64777 puts out the i and q component of its signal on two separate analog output interfaces (see figure 3.1). the output interface contains two internal 10-bit digital-to-analog converters. bit 6, msb bit 5 bit 4 bit 3 bit 2 bit 1 bit 0, lsb 1 1010 sb_base.1 sb_base.0
3-4 interfaces figure 3.1 analog i/q output interface diagram figure 3.2 shows a typical application for interfacing with the outputs of the two L64777 dacs. avdd1/comp1 vref1 10-bit dac 10 avss2 avdd2comp2 differential q output differential i output vss avss1 r vddx1 3 on-chip off-chip qam_i, qam_in qam_q, qam_qn q filter output i filter output functional (test mode is selected using vref2 vddx2 10 10-bit dac r 3 2 10 test bus ft mode pins)
analog output interface 3-5 figure 3.2 i and q dac filter diagrams 5 v a f c17 10 m f/16 v + c18 0.1 th2 th th1 th qam_i qam_in 11 r13 221 r169 470 u4 r14 r17 221 1 2 3 4 nc in - in + - vs - + nc - vs out nc 8 7 6 5 f th4 th 1 r18 51 ad8048ar f r19 51 f r20 51 f r21 511 f + c35 10 m f/16 v c34 0.1 - 5 v a 5 v a f c42 10 m f/16 v + c43 0.1 th8 th th7 th qam_q qam_qn 11 r35 221 r36 511 u8 r39 221 1 2 3 4 nc in - in + - vs - + nc + vs out nc 8 7 6 5 f th9 th 1 r40 51 ad8048ar f r41 51 f r42 51 f r43 511 f + c59 10 m f/16 v c58 0.1 - 5 v a 100
3-6 interfaces the device has separate differential outputs for the i and q component. the differential outputs terminate externally (that is, the external components must provide termination to both differential lines, and the dac achieves maximum linearity in differential mode). 3.4 digital output interface the L64777 i and q component outputs are available in 10-bit digital format. depending on the pll mode, either oclk or pclk is the related clock. the output format can be programmed either as a twos complement, or as a sine magnitude representation.
L64777 dvb qam modulator technical manual 4-1 chapter 4 register descriptions this chapter describes registers used to con?gure and monitor the L64777. the sections in this chapter are: section 4.1, group 2 general-purpose registers, page 4-1 section 4.2, nco-related registers, page 4-10 4.1 group 2 general-purpose registers the registers listed in table 4.1 and described subsequently comprise the group 2 registers. these registers con?gure and monitor the operations of the L64777. (note that the L64777 does not use groups 1, 3C7.) the ?lter coef?cient register a0 is a sequential input register, which sequentially shifts in the 196 bytes of ?lter coef?cients. therefore, the external microprocessor must make exactly 196 accesses to that register. to verify the ?lter coef?cients, read back the contents of register 0 after writing each coef?cient. this does not in?uence the shift register shift operation. the remaining registers can be either loaded or read back at random. the address is speci?ed by writing it into the group 0 address pointer register. all 43 registers of the L64777 are 8-bit. table 4.1 provides an overview of the bit allocations for the L64777 registers. note that an r in column a indicates a read-only register; an rw indicates a read/write register.
4-2 register descriptions table 4.1 group 2 bit allocation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a fcoeff.7 fcoeff.6 fcoeff.5 fcoeff.4 fcoeff.3 fcoeff.2 fcoeff.1 fcoeff.0 r/w 0 serin newsync extsync pllset freq_pha se msize.2 msize.1 msize.0 r/w 1 reserved fdel.6 fdel.5 fdel.4 fdel.3 fdel.2 fdel.1 fdel.0 r/w 2 smag reserved iq_ex reserved scr_off rs_off int_off reserved r/w 3 sync_ length.7 sync_ length.6 sync_ length.5 sync_ length.4 sync_ length.3 sync_ length.2 sync_ length.1 sync_ length.0 r/w 4 sync_ byte.7 sync_ byte.6 sync_ byte.5 sync_ byte.4 sync_ byte.3 sync_ byte.2 sync_ byte.1 sync_ byte.0 r/w 5 auto- reset pll_inv iram_off fifo_off diff_off map_off ampl reserved r/w 6 icnt_o.7 icnt_o.6 icnt_o.5 icnt_o.4 icnt_o.3 icnt_o.2 icnt_o.1 icnt_o.0 r/w 7 reserved icnt_o.14 icnt_o.13 icnt_o.12 icnt_o.11 icnt_o.10 icnt_o.9 icnt_o.8 r/w 8 icnt_i.7 icnt_i.6 icnt_i.5 icnt_i.4 icnt_i.3 icnt_i.2 icnt_i.1 icnt_i.0 r/w 9 reserved i_icnt_i.14 icnt_i.13 icnt_i.12 icnt_i.11 icnt_i.10 icnt_i.9 icnt_i.8 r/w 10 track- steps.1 track- steps.0 uncon- str. input gap.4 gap.3 gap.2 gap.1 gap.0 r/w 11 syncok syncok_ store fifo_ alarm_ store erf_ store nco event mask_erf mask_ syncok mask_fifo _alarm r/w 12 reserved below_ thres measure_ done step_ update auto_ acqui_ running acq_state .2 acq_state .1 acq_state .0 r13 reserved start measure- ment enable_ nco_loop mask_nco _irq auto_ acquisitio n_on mask_acq _irq en_phase _loop fifo_int r/w 14 test.7 test.6 test.5 test.4 test.3 test.2 test.1 test.0 r/w 15 inistep.7 inistep.6 inistep.5 inistep.4 inistep.3 inistep.2 inistep.1 inistep.0 r/w 16 inistep.15 inistep.14 inistep.13 inistep.12 inistep.11 inistep.10 inistep.9 inistep.8 r/w 17 inistep.23 inistep.22 inistep.21 inistep.20 inistep.19 inistep.18 inistep.17 inistep.16 r/w 18 nco_gain. 7 nco_gain. 6 nco_gain. 5 nco_gain. 4 nco_gain. 3 nco_gain. 2 nco_gain. 1 nco_gain. 0 r/w 19 nco_gain. 15 nco_gain. 14 nco_gain. 13 nco_gain. 12 nco_gain. 11 nco_gain. 10 nco_gain. 9 nco_gain. 8 r/w 20
group 2 general-purpose registers 4-3 ref_dur.7 ref_dur.6 ref_dur.5 ref_dur.4 ref_dur.3 ref_dur.2 ref_dur.1 ref_dur.0 r/w 21 ref_dur. 15 ref_dur .14 ref_dur. 13 ref_dur. 12 ref_dur. 11 ref_dur. 10 ref_dur.9 ref_dur.8 r/w 22 prob_dur. 7 prob_dur. 6 prob_dur. 5 prob_dur. 4 prob_dur. 3 prob_dur. 2 prob_dur. 1 prob_dur. 0 r/w 23 prob_dur. 15 prob_dur. 14 prob_dur. 13 prob_dur. 12 prob_dur. 11 prob_dur. 10 prob_dur. 9 prob_dur. 8 r/w 24 n_pclk.7 n_pclk.6 n_pclk.5 n_pclk.4 n_pclk.3 n_pclk.2 n_pclk.1 n_pclk.0 r 25 nm_count. 7 nm_count. 6 nm_count. 5 nm_count. 4 nm_count. 3 nm_count. 2 nm_count. 1 nm_count. 0 r26 nm_count. 15 nm_count. 14 nm_count. 13 nm_count. 12 nm_count. 11 nm_count. 10 nm_count. 9 nm_count. 8 r27 nm_count. 23 nm_count. 22 nm_count. 21 nm_count. 20 nm_count. 19 nm_count. 18 nm_count. 17 nm_count. 16 r28 n_count.7 n_count.6 n_count.5 n_count.4 n_count.3 n_count.2 n_count.1 n_count.0 r 29 n_count. 15 n_count. 14 n_count. 13 n_count. 12 n_count. 11 n_count. 10 n_count.9 n_count.8 r 30 n_count. 23 n_count. 22 n_count. 21 n_count. 20 n_count. 19 n_count. 18 n_count. 17 n_count. 16 r31 np_count. 7 np_count. 6 np_count. 5 np_count. 4 np_count. 3 np_count. 2 np_count. 1 np_count. 0 r32 np_count. 15 np_count. 14 np_count. 13 np_count. 12 np_count. 11 np_count. 10 np_count. 9 np_count. 8 r33 np_count. 23 np_count. 22 np_count. 21 np_count. 20 np_count. 19 np_count. 18 np_count. 17 np_count. 16 r34 cur_step.7 cur_step.6 cur_step.5 cur_step.4 cur_step.3 cur_step.2 cur_step.1 cur_step.0 r 35 cur_step. 15 cur_step. 14 cur_step. 13 cur_step. 12 cur_step. 11 cur_step. 10 cur_step.9 cur_step.8 r 36 cur_step. 23 cur_step. 22 cur_step. 21 cur_step. 20 cur_step. 19 cur_step. 18 cur_step. 17 cur_step. 16 r37 cur_upd.7 cur_upd.6 cur_upd.5 cur_upd.4 cur_upd.3 cur_upd.2 cur_upd.1 cur_upd.0 r 38 cur_upd. 15 cur_upd. 14 cur_upd. 13 cur_upd. 12 cur_upd. 11 cur_upd. 10 cur_upd.9 cur_upd.8 r 39 fifo_full. 7 fifo_full. 6 fifo_full. 5 fifo_full. 4 fifo_full. 3 fifo_full. 2 fifo_full. 1 fifo_full.0 r 40 ph_gain.7 ph_gain6 ph_gain.5 ph_gain.4 ph_gain.3 ph_gain.2 ph_gain.1 ph_gain.0 r/w 41 ext_gap.7 ext_gap.6 ext_gap.5 ext_gap.4 ext_gap.3 ext_gap.2 ext_gap.1 ext_gap.0 r/w 42 thresh- old.7 thresh- old.6 thresh- old.5 thresh- old.4 thresh- old.3 thresh- old.2 thresh- old.1 thresh- old.0 r/w 43 table 4.1 group 2 bit allocation (cont.) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a
4-4 register descriptions 4.1.1 register 0 fcoeff filter coef?cient shift r/w [7:0] writing to this location shifts the 196-byte ?lter coef?cient shift register forward by one and puts this entry at the end of the queue. reading this location shows the last entry of the coef?cient shift register without shifting it. the reset values for the bit ?elds in this register are 0. 4.1.2 register 1 serin serial/parallel input setting r/w 7 when this bit is 1, the L64777 uses din[0] as serial input and considers iclk as a bit clock. when this bit is 0, the L64777 uses din[7:0] as parallel input and iclk as a byte clock. the reset value is 0. newsync newsync insertion r/w 6 when this bit is 1, the L64777 inserts a new sync word (newsync, see section 2.6.1) into the data stream. when this bit is 0, the L64777 leaves the data stream unchanged. the reset value is 1. extsync synchronization setting r/w 5 when this bit is 1, the L64777 synchronizes positive pulses on the fstartin pin. when this bit is 0, the L64777 synchronizes on sync_byte in the input stream. the reset value is 0. pllset pll divider setting r/w 4 when this bit is 1, the L64777 forces a load of pll dividers. when this bit is 0, the L64777 runs the pll dividers normally. the reset value is 0. freq_phase frequency/phase compare r/w 3 when this bit is 1, the L64777 uses frequency compare for external vco control. when this bit is 0, the L64777 uses phase compare. the reset value is 1. 7 0 fcoeff 7654 3 2 0 serin newsync extsync pllset freq_phase msize
group 2 general-purpose registers 4-5 msize symbol size r/w [2:0] this value indicates the size of symbols: 0b000 = 1 bit 0b001 = 2 bit 0b010 = 3 bit 0b011 = 4 bit 0b100 = 5 bit 0b101 = 6 bit 0b110 = 7 bit 0b111 = 8 bit. the reset value is 0b101 4.1.3 register 2 res reserved 7 this bit is reserved. fdel fifo delay r/w [6:0] this parameter indicates the fifo delay value in the gray code. writing to this location loads the iclk address counter with 0 and the oclk-driven address counter to the fdel value. if the fifo is automatically reset, the L64777 also uses this value for the oclk-driven address. the reset value is 0b110 0000. 4.1.4 register 3 smag sign magnitude r/w 7 when this bit is 0, the L64777 outputs a twos complement at the nyquist ?lter. when this bit is 1, the L64777 inverts the sign bit and the output sign magnitude representation. the reset value is 0. res reserved 6, 4, 0 these bits are reserved. 76 0 res fdel 76543210 smag res iq_ex res scr_off rs_off int_off res
4-6 register descriptions iq_ex i and q channel exchange r/w 5 when this bit is 1, the L64777 exchanges the i and q channels at the nyquist ?lter input. when this bit is 0, the L64777 leaves the data stream unchanged. the reset value is 0. scr_off scrambler off r/w 3 when this bit is 1, the L64777 stops the scrambler and delays the data in this module by three clock cycles. when this bit is 0, the scrambler runs normally. the reset value is 0. rs_off reed-solomon off r/w 2 when this bit is 1, the L64777 stops the reed solomon (rs) encoder and delays the data in this module by two clock cycles. when this bit is 0, the L64777 runs the rs encoder normally. the reset value is 0. int_off interleaver off r/w 1 when this bit is 1, the L64777 stops the interleaver and delays the data in this module by three clock cycles. when this bit is 0, the L64777 runs the interleaver in dvb-compliant mode. the reset value is 0. 4.1.5 register 4 sync_length sync block length r/w [7:0] this register speci?es the distance between consecutive sync_byte values. legal register values range from 32 to 255 for sync block length. the reset value is 0b1011 1011. 4.1.6 register 5 sync_byte sync reference pattern r/w [7:0] this register speci?es the sync reference pattern. the reset value is 0b0100 0111. 76543210 sync_length 76543210 sync_byte
group 2 general-purpose registers 4-7 4.1.7 register 6 autoreset automatic reset setting r/w 7 when this bit is 1, the L64777 loads the fifo address counters with the initial values in register 2 after the detection of a fifo alarm (pointer collision). when this bit is 0, the fifo address counters remain unchanged after a pointer collision until an external microcontroller intervenes. the reset value is 1. pll_inv phase detector setting r/w 6 when this bit is 1, the L64777 exchanges the reference and feedback inputs of the frequency and phase detector. when this bit is 0, no exchange takes place. the reset value is 0. iram_off interleaver ram off r/w 5 when this bit is 1, the L64777 switches the interleaver ram off after reset and initializes the ram with 0 values (not with the incoming data stream). the interleaver ram resumes normal operation as soon as the ?rst sequence start from the sstartin pin (pin 90) comes in the data stream. this setting is useful for getting a well-de?ned chip output sequence. when this bit is 0, the L64777 uses the interleaver ram in dvb-compliant mode on the input data stream. the reset value is 1. fifo_off fifo off r/w 4 when this bit is 1, the L64777 switches the fifo input stage off and clocks the input data stream through three internal registers from the iclk to the oclk domain. when this bit is 0, the L64777 uses normal fifo processing and delay. the reset value is 0. note: this mode requires iclk to be exactly the same signal as oclk. you must connect these pins to each other. diff_off differential encoding off r/w 3 when this bit is 1, the L64777 switches the differential encoding off. when this bit is 0, the L64777 encodes according to the dvb standard. the reset value is 0. 76543210 autoreset pll_inv iram_off fifo_off diff_off map_off ampl res
4-8 register descriptions map_off qam mapping off r/w 2 when this bit is 1, the L64777 stops qam mapping. when this bit is 0, the L64777 uses dvb-compliant mapping. the reset value is 0. ampl pll oscillator amplitude r/w 1 this controls the amplitude of the on-chip pll oscillator. when this bit is 0, the L64777 is in low-power mode with higher jitter. when this bit is 1, the L64777 is in high-power mode with lower jitter. for normal operation, set this bit to 0. res reserved 0 this bit is reserved. 4.1.8 registers 7 and 8 res reserved 15 this bit is reserved. icnt_o initial oclk value r/w [14:0] this is a 15-bit initial value for the oclk pll feedback division. the reset value for bit 3 is 1; for all other bits it is 0. 4.1.9 registers 9 and 10 res reserved 15 this bit is reserved. icnt_i initial iclk value r/w [14:0] this is a 15-bit initial value for the iclk pll reference division. the reset value for bit 1 is 1; for all other bits it is 0. 15 14 0 res icnt_o 15 14 0 res icnt_i
group 2 general-purpose registers 4-9 4.1.10 register 11 tracksteps steps to sync r/w [7:6] this value indicates the number of steps to acquire synchronization and to declare loss of sync if the sync pattern is missing for this number of events: 0b00 = 3 0b01 = 4 0b11 = 5 the reset value is 0b00. unconst. input unconstrained input r/w 5 the default setting of this bit is 0, which indicates that a frame structure with a sync byte is required after every (block length - 1) bytes. if this bit is 1, any data stream is accepted. the reset value is 0. gap rs code bytes r/w [4:0] this is the number of bytes to be inserted for the rs code at each end of a sync block. if the value is 0, there is no modi?cation of the incoming data stream. the maximum value is 31 bytes to insert. this control generates the gaps in the incoming stream for rs code insertion. at the end of each block, readout of the fifo stops for the speci?ed number of bytes. this determines the value of fdel (register 2). the gap parameter determines the number of bytes inserted into the symbol stream, but not read from the fifo. these bytes come from the rs encoder; thus, the setting must be 16 (or 18 for the proprietary mode). the reset value is 0b10000. 7654 0 tracksteps unconst. input gap
4-10 register descriptions 4.2 nco-related registers 4.2.1 register 12 syncok state of syncok pin r/w 7 this value re?ects the actual state of the syncok pin. this signal is slow enough to be sampled by the external microcontroller. when this bit is 1, sync is achieved. when this bit is 0, sync is not achieved. the reset value is 0. syncok_store r 6 this read-only bit is set to 1 if a faulty syncok condition is detected since the last read. if this bit is 0, it indicates that the sync lock status continues to be positive. the reset value is 0. fifo_alarm_store r 5 this read-only bit is set to 1 if a fifo alarm condition is detected since the last read. if this bit is 0, no fifo alarm condition was detected. the reset value is 0. erf_store error flag store r 4 this read-only bit is set to 1 if an error ?ag is inserted since the last read. if this bit is 0, no error ?ag was inserted. the reset value is 0. nco_event r/w 3 if this bit is 1, the nco measurement is complete or the auto acquisition has terminated. the reset value is 0. mask_erf error flag mask r/w 2 if this bit is 1, an error ?ag insertion in the mpeg transport packet does not generate an interrupt. if this bit is 0, an error ?ag insertion does generate an interrupt. the reset value is 0. 76543210 syncok syncok _store fifo_alarm _store erf_store nco_event mask_erf mask_sync ok mask_fifo _alarm
nco-related registers 4-11 mask_syncok 1 if this bit is 1, a missing syncok does not generate an interrupt. if this bit is 0, a missing syncok generates an interrupt. the reset value is 0. mask_fifo_alarm 0 if this bit is 1, a fifo alarm (pointer collision) does not generate an interrupt. if this bit is 0, a fifo alarm (pointer collision) generates an interrupt. the reset value is 0. 4.2.2 register 13 res reserved r 7 this bit is reserved. below_thres fifo content threshold r 6 when this bit is 1, the virtual fifo content is below or equal to the threshold programmed in register 43. during auto_acquisition, the threshold is dynamically changed. the reset value is 0. measurement_done r 5 a 1 in this bit indicates that the measurement data gained during byte clock probe are valid and that the measurement is complete. the reset value is 0. step_update r 4 a 1 in this bit indicates a step update since the last reading of the register. this is relevant only during nco acquisition mode. the reset value is 0. auto_acqui_running r 3 a 1 in this bit indicates that the internal frequency acquisition is running. the reset value is 0. acq_state internal acquisition state r [2:0] this indicates how many auto acquisition loops have taken place since the initiation of the auto acquisition mode. the reference duration has a length of two acq_state input packets, and the threshold is divided by two acq_state times. the reset value is 0b111. 765432 0 res below_ thres measurement_ done step_ update auto_acqui_ running acq_state
4-12 register descriptions 4.2.3 register 14 res reserved 7 this bit is reserved. start_measurement r/w 6 a transition from 0-to-1 starts a measurement of the byte clock connected to the iclk input. measurement_ done in status register (13) indicates the end of the measurement. the reset value is 0. enable_nco_ loop r/w 5 setting this bit allows a step update in the nco loop based on the fifo fullness. the ref_dur parameter can adjust the update frequency. the reset value is 0. mask_nco_irq r/w 4 setting this bit enables the interrupt for the measurement_done event. even in the case of a disabled interrupt, the status is indicated correctly. the reset value is 0. auto_acquisition_on r/w 3 a 1-to-0 transition in this bit starts an internal procedure to regulate the nco frequency. the reset value is 0. setting this bit to 1 activates the autoacquisition mode. mask_acq_irq r/w 2 if this bit is 1, a transition from 1 to 0 in the auto_acqui_running bit of register 13 causes an interrupt. the interrupt is visible in the nco_event bit of register 12 and clears upon the reading of register 13. the reset value is 0. en_phase_loop r/w 1 setting this bit enables the phase acquisition loop, after autofrequency acquisition is completed in the nco mode of operation. the reset value is 0. 76543210 res start_ measure- ment enable_ nco_loop mask_nco_ irq auto_ acuisition _on mask_acq_ irq en_phase_ loop fifo_int
nco-related registers 4-13 fifo_int fifo interrupt r/w 0 this bit enables generation of an interrupt in response to a fifo alarm. the reset value is 0. 4.2.4 register 15 test reserved test r/w [7:0] this register is reserved for lsi logic production testing; each bit ?eld must be set to zero. the reset value is 0. 4.2.5 registers 16, 17, and 18 init_step r/w [23:0] this value is the initial nco step parameter. it is loaded into the nco when the most signi?cant portion is written. these are nco-related register ?elds; they are used only in pll mode. bits 8 and 23 are reset to 0; all other bits are reset to 1. 4.2.6 registers 19 and 20 nco_gain nco loop bandwidth adjustment r/w [15:0] the L64777 can use this parameter to adjust the nco loop bandwidth. the value becomes valid on writing to the most signi?cant portion. these are nco-related register ?elds; they are used only in pll mode 2. bit 8 is reset to 1; all other bits are reset to 0. 7 0 test 23 0 init_step 15 0 nco_gain
4-14 register descriptions 4.2.7 registers 21 and 22 ref_dur duration between nco step updates r/w [15:0] this parameter determines the duration between the nco step updates in multiples of the sync length. these are nco-related register ?elds; they are used only in pll mode 2. bit 0 resets to 1; all other bits reset to 0. 4.2.8 registers 23 and 24 prob_dur byte clock duration r/w [15:0] this parameter determines the duration for the byte clock measurement in units of 256 iclk cycles. these are nco-related register ?elds; they are used only in pll mode 2. the reset value is 0. 4.2.9 register 25 n_pclk pclk cycles r/w [7:0], r this is the number of pclk cycles during one iclk byte clock. the value in this register is valid only if the measurement_done bit in the nco control register is set. these are nco-related register ?elds; they are used only in pll mode 2. the reset value is 0. 4.2.10 registers 26, 27, and 28 nm_count r [23:0] this value is the number of clk cycles found within the duration of the (n - 1) pclk cycles. the value in this 15 0 ref_dur 15 0 prob_dur 7 0 n_pclk 23 0 nm_count
nco-related registers 4-15 register is valid only if the measurement_done bit in the nco control register is set. these are nco-related register ?elds; they are used only in pll mode 2. the reset value is 0. 4.2.11 registers 29, 30, and 31 n_count iclk cycles r [23:0] this value is the number of iclk cycles found within the duration of n pclk cycles. the value in this register is valid only if the measurement_done bit in the nco control register is set. these are nco-related register ?elds; they are used only in pll mode 2. the reset value is 0. 4.2.12 registers 32, 33, and 34 np_count r [23:0] this value is the number of iclk cycles found within the duration of (n + 1) pclk cycles. the value in this register is valid only if the measurement_done bit in the nco control register is set. these are nco-related register ?elds; they are used only in pll mode 2. the reset value is 0. 4.2.13 registers 35, 36, and 37 cur_step current nco loop step r [23:0] this value indicates the current nco loop step. it differs from the programmed update step if autoacquisition is enabled. the registers are read-only. these are nco-related register ?elds; they are used only in pll mode 2. the reset value is 0. 23 0 n_count 23 0 np_count 23 0 cur_step
4-16 register descriptions 4.2.14 registers 38 and 39 cur_upd current nco loop update step r [15:0] this value indicates the current nco loop update step. it differs from the programmed update step if autoacquisi- tion is enabled. the registers are read-only. these are nco-related register ?elds; they are used only in pll mode 2. the reset value is 0. 4.2.15 register 40 fifo_full fifo fullness indicator r [7:0] this value is a sign representation of the virtual fifo fullness used for the nco loop regulation. these are nco-related register ?elds; they are used only in pll mode 2. the reset value is 0. 4.2.16 register 41 ph_gain phase regulation gain r/w [7:0] this value sets the gain used during phase regulation. the real value applied is multiplied by four. these are nco-related register ?elds; they are used only in pll mode 2. the reset value is 0b0001 0000. 15 0 cur_upd 7 0 fifo_full 7 0 ph_gain
nco-related registers 4-17 4.2.17 register 42 ext_gap gap bytes r/w [7:0] this value indicates the number of gap bytes applied to the ts input. these are nco-related register ?elds; they are used only in pll mode 2. the reset value is 0b0100 0110. 4.2.18 register 43 threshold fifo measurement threshold r/w [7:0] this value sets the threshold for the virtual fifo measurement, which is used as the initial value for the autoacquisition. these are nco-related register ?elds; they are used only in pll mode 2. the reset value is 0b0111 0011 table 4.2 shows the reset values for all register ?elds. 7 0 ext_gap 7 0 threshold table 4.2 reset values for register fields bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a 000000000 010011011 011000002 000000003 101110114 010001115 101000016 000010007 000000008 000000109 0000000010 0001000011
4-18 register descriptions 0000000012 0000011113 0000000014 0000000015 1111111116 1111111017 0111111118 0000000019 0000000120 0000000121 0000000022 0000000023 0000000024 0000000025 0000000026 0000000027 0000000028 0000000029 0000000030 0000000031 0000000032 0000000033 0000000034 0000000035 0000000036 0000000037 0000000038 0000000039 0000000040 0001000041 0100011042 0111001143 table 4.2 reset values for register fields (cont.) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a
L64777dvb qam modulator technical manual 5-1 chapter 5 signals this chapter de?nes the signals for the L64777. it consists of the following sections: section 5.1, overview, page 5-1 section 5.2, mpeg transport stream multiplexer signals, page 5-3 section 5.3, status information signals, page 5-4 section 5.4, test signals, page 5-5 section 5.5, control signals, page 5-6 section 5.6, external pll signals, page 5-6 section 5.7, analog qam signals, page 5-7 section 5.8, serial microprocessor interface signals, page 5-8 5.1 overview figure 5.1 shows the L64777 interface signals in their respective groupings. within each category, the signals are described in alphabetical order by signal mnemonic.
5-2 signals figure 5.1 logic symbol for the L64777 errorin qam_i firstout oclk reset_n dvalidin serial microprocessor control signals mpeg ts analog din[7:0] L64777 qam modulator iclk fstartout pll_out_cs sstartin testpins[11:0] syncok fstartin fifoalarm qam_q pll_mode[1:0] scl sda sb_base[1:0] avss1 avdd1 comp1 avss2 avdd2 comp2 vref_i iref1 iref2 vss vdd external pll signals status information int_n sclk pclk dig_q[9:0] dig_i[9:0] vref_q vddx_i vddx_q 2 interface mux and test qam qam_qn qam_in
mpeg transport stream multiplexer signals 5-3 5.2 mpeg transport stream multiplexer signals din[7:0] qam modulator parallel/serial data in input serial data enters the L64777 on din[0]; parallel data enters on din[7:0]. the modulator samples din[7:0] at the positive edge of iclk. the din[7:0] input accepts data with any number of invalid bits in between. the modulator disregards invalid bits or bytes and does not take them into the input fifo. dvalidin clock enable input input when dvalidin is active (high), the L64777 accepts data from din[7:0] on a continuous basis. when dvalidin is low, data input to the internal fifo and internal data processing stops, and the encoder does not accept new input from the din[7:0] pins. dvalidin functions independently of the modulator. errorin error detection flag input the errorin pin is asserted to ?ag uncorrectable errors. the L64777 checks the errorin status at the ?rst bit of a frame; then, if required (high = set error bit), it copies the value of that bit to the mpeg error-indication bit. fstartin external sync input input the fstartin pin is asserted to mark the beginning of an mpeg transport packet by a hardwired signal. if the incoming bitstream contains no unique sync words, this pulse must be applied to the L64777. the L64777 forces synchronization with fstartin pulses into the chip; it does not ?ywheel-stabilize synchronization as in the sync word detection mode. in the sync insertion mode, the L64777 regenerates the dvb-de?ned sync information and inserts it into the qam modulator. iclk qam modulator input clock input iclk is a positive-edge-triggered clock. the L64777 clocks din[7:0], dvalidin, errorin, fstartin and sstartin on the rising edge of iclk. iclk is either a byte clock or a bit clock, depending on the control register (register 1) setup for parallel/serial mode.
5-4 signals sclk modulator symbol clock output output sclk is a clock output synchronous to internally processed symbols and bytes; it is identical to oclk/4. the L64777 uses sclk to determine the phase of the nyquist ?lter output. the rising edge of sclk is followed by phase 0. the falling edge is the transition of phase 1 to phase 2 in 4-fold oversampling mode. sstartin sync sequence start input the sstartin pin is asserted to mark the beginning of a new, fully reset sequence by a hardwired signal. the L64777 evaluates the sstartin negative slope and restarts all internal sequences at the next block/frame start following the negative sstartin slope. if no sstartin is applied, all internal sequences run free after the reset. 5.3 status information signals dig_i[9:0] digital i component output this port provides modulator i-component output in digital format. depending on the pll mode, either oclk or pclk is the related clock. dig_q[9:0] digital q component output this port provides modulator q-component output in digital format. depending on the pll mode, either oclk or pclk is the related clock. fifoalarm fifo collision detected output if this alarm occurs, the fifo control has detected equal pointers for read and write access. a detected collision most probably indicates unlocked external pll-vco circuitry. the L64777 synchronizes this signal with sclk-driven ?ip-?ops for the output. firstout first block of new sequence out output firstout occurs together with fstartout and indicates the head of a sync block that has just-reset sequences, as controlled by sstartin. firstout is the acceptance of a sstartin negative slope delayed by all internal processing modules.
test signals 5-5 fstartout frame start output output fstartout is asserted during the ?rst symbol in every sync frame. the width of fstartout re?ects the number of bytes that the gap parameter inserts. a one-cycle width indicates no inserted gaps; a width of 17 means 16 inserted bytes as an reed-solomon gap. fstartout is applied only in sync word detection mode. if fstartin pulses force synchronization, fstartout is constantly low. syncok sync detection/phase monitoring output in internal sync mode, this pin indicates undisturbed synchronization status when high. this signal is asserted when the number of track steps required for synchronization is ful?lled. if fstartin pulses force synchronization, syncok is constantly low. 5.4 test signals ftmode[2:0] functional test bus input these must be tied to 0. iddtn[3] idd test mode input iddtn is a production test pin. nt_out[4] nand tree output output nt_out is a production test pin. scan_enable[5] scan enable input this pin enables scan chain shift. tnn[11] test output enable input tnn switches all 3-state buffers to high-impedance mode for testing. trstn[10] test reset input reset for the jtag unit. tms[9] test mode select input tms selects the jtag unit test mode. tdo[8] test data output output tdo is the jtag unit data output.
5-6 signals tdi[7] test data input input tdi is the jtag unit data input. tck[6] test mode clock input tck is the jtag test mode clock. 5.5 control signals oclk encoder out/processing clock in bidirectional oclk is a positive-edge-triggered clock. the L64777 internally processes data based on a fraction of oclk (for example: scrambler, interleaver, reed-solomon encoder) and references data outputs (i, q, fstartout) to oclk. pll_mode[1:0] select pll mode input to select the pll mode: 0b00 or 0b01 for external pll usage 0b11 for nco usage reset_n reset input this pin resets all internal data paths. reset timing is asynchronous to the device clocks. reset affects all the con?guration registers and the ?lter coef?cients, which must be downloaded again after reset. 5.6 external pll signals pclk processing clock: pll mode 2 input the pclk output of the l64724 provides this clock, which drives the digital signal processing of interpolation and the nco. when using mode 1, leave this pin open. pll_out_cs pll current source 3-state output this pin is a charge pump for an external pll low pass to control frequency. the comparator is frequency- and phase-sensitive. the pin is normally on 3-state z level and drives positive and negative current, as required. depending on the con?guration, the current source can be inverted.
analog qam signals 5-7 5.7 analog qam signals avdd1 analog vdd input: i component dac analog input for usage and value, see the lsi logic datasheet g10 ? -p cw900100 10-bit direct digital synthesis digital- to-analog converter (september 1998). avdd2 analog vdd input: q component dac analog input for usage and value, see the lsi logic datasheet g10 ? -p cw900100 10-bit direct digital synthesis digital- to-analog converter (september 1998). avss1 analog vss input: i component dac analog input for usage and value, see the lsi logic datasheet g10 ? -p cw900100 10-bit direct digital synthesis digital- to-analog converter (september 1998). avss2 analog vss input: q component dac analog input for usage and value, see the lsi logic datasheet g10 ? -p cw900100 10-bit direct digital synthesis digital- to-analog converter (september 1998). comp1 compensation output: i comp. dac analog output for usage and value, see the lsi logic datasheet g10 ? -p cw900100 10-bit direct digital synthesis digital- to-analog converter (september 1998). comp2 compensation output: q comp. dac analog output for usage and value, see the lsi logic datasheet g10 ? -p cw900100 10-bit direct digital synthesis digital- to-analog converter (september 1998). iref1 reference current: i component dac analog input for usage and value, see the lsi logic datasheet g10 ? -p cw900100 10-bit direct digital synthesis digital- to-analog converter (september 1998). iref2 reference current: q component dac analog input for usage and value, see the lsi logic datasheet g10 ? -p cw900100 10-bit direct digital synthesis digital- to-analog converter (september 1998). qam_i symbol i modulation analog output qam_i is the positive differential analog in-phase output signal of the modulator.
5-8 signals qam_in symbol i modulation inverted analog output qam_in is the corresponding inverted differential part to qam_i. qam_q symbol q modulation analog output qam_q is the positive differential analog quadrature output signal of the modulator. qam_qn inverted differential of qam_q analog output qam_qn is the corresponding inverted differential part to qam_q. vddx_i isolated power: digital-to-analog converter, i channel for usage and value, see the lsi logic datasheet g10 ? -p cw900100 10-bit direct digital synthesis digital- to-analog converter (september 1998). vddx_q isolated power: digital-to-analalog converter, q channel for usage and value, see the lsi logic datasheet g10 ? -p cw900100 10-bit direct digital synthesis digital- to-analog converter (september 1998). vref_i reference voltage input: i analog input for usage and value, see the lsi logic datasheet g10 ? -p cw900100 10-bit direct digital synthesis digital- to-analog converter (september 1998). vref_q reference voltage input: q analog input for usage and value, see the lsi logic datasheet g10 ? -p cw900100 10-bit direct digital synthesis digital- to-analog converter (september 1998). 5.8 serial microprocessor interface signals int_n interrupt request output the L64777 asserts int_n low when the interrupt is enabled and an interrupt condition occurs. int_n is an open drain output that requires an external pull-up resistor for operation.
serial microprocessor interface signals 5-9 sb_base[1:0] serial bus base address input the external microprocessor must apply these two signals as static signals to the device because they determine the two lsbs of the serial bus base address. scl serial clock line input in conjunction with sda, scl controls the microprocessor interface according to the protocol described in appendix a. sda serial data access bidirectional in conjunction with scl, sda controls the microprocessor interface according to the protocol described in appendix a.
5-10 signals
L64777 dvb qam modulator technical manual 6-1 chapter 6 speci?cations this chapter provides information about the electrical ratings, pins, and packaging for the L64777. it consists of the following sections: section 6.1, ac/dc speci?cations, page 6-1 section 6.2, pin descriptions and lists, page 6-5 section 6.3, package pinout, page 6-10 6.1 ac/dc speci?cations this section lists the electrical requirements, provides the ac timing characteristics, shows the ac timing diagrams, and lists the ac timing values for the L64777 decoder. 6.1.1 electrical ratings the tables in this section specify the electrical requirements for the L64777 decoder. table 6.1 provides the L64777 absolute maximum electrical and temperature ratings. table 6.2 provides the L64777 recommended operating conditions. table 6.3 lists the dc characteristics for the L64777.
6-2 speci?cations when studying the values in table 6.3, note that the L64777 follows the lsi logic g10-p process, which is characterized by a 0.35-micron gate length. table 6.1 L64777 absolute maximum ratings symbol parameter limits unit v dd dc supply - 0.3 to 3.9 v v in lvttl input voltage - 1.0 to v dd + 0.3 v v in 5 v compatible inputs - 1.0 to 6.5 v i in dc input current 10 ma t stg storage temperature range (plastic) - 40 to +150 c t j operating junction temperature range 0 to +125 c table 6.2 L64777 recommended operating conditions symbol parameter limits unit v dd dc supply + 3.14 to + 3.45 v t a ambient temperature 0 to + 70 c table 6.3 L64777 dc characteristics symbol parameter condition 1 min typ max units v dd supply voltage 3.14 3.3 3.45 v v il input voltage low vss - 0.5 0.8 v v ih input voltage high 2.0 v dd + 0.3 v v oh output voltage high i oh = - 4.0 ma 2.4 v dd v v ol output voltage low i ol = 4.0 ma 0.2 0.4 v i oz current 3-state leakage w/pulldown v dd = max, v out = v ss or v dd - 10 110 m a
ac/dc speci?cations 6-3 6.1.2 ac timing diagrams for L64777 figure 6.1 illustrates the ts input timing. figure 6.1 ts input timing figure 6.2 illustrates the reset timing of the L64777. figure 6.2 L64777 reset timing diagram figure 6.3 illustrates the 3-state delay timing of the L64777 bus. i in input current leakage v dd = max, v in = v dd or v ss - 10 110ma i in input current leakage w/pullup v dd = max, v in = v dd or v ss - 62 - 215 - 384 ma i in input current leakage w/pulldown v dd = max, v in = v dd or v ss - 62 - 215 - 384 ma i dd quiescent supply current v in =v dd or v ss 2ma i cc dynamic supply current iclk = 54 mhz max, pll mode 2 pclk 90 mhz vdd = max 50 ma 1. speci?ed at v dd = 3.3 v 5% at ambient temperature over the speci?ed range. table 6.3 L64777 dc characteristics (cont.) symbol parameter condition 1 min typ max units inputs 3 & 6 2 & 5 1 & 4 8 7 iclk reset 9 10
6-4 speci?cations figure 6.3 L64777 bus 3-state delay timing the numbers in column 1 of table 6.4 refer to the timing parameters in the preceding ?gures. all parameters in this table apply for t a =0 cto 85 c, v dd = 3.1 v to 3.6 v, and an output load of 50 pf. tn data 11 11 table 6.4 L64777 preliminary timing parameters no. parameter description min max unit 1 tcycle clock cycle oclk 32 C ns 2 tpwh clock pulse width high oclk 7 C ns 3 tpwl clock pulse width low oclk 7 C ns 4 ti_cycle clock cycle iclk 18.5 C ns 5 ti_pwh clock pulse width high iclk 9 C ns 6 ti_pwl clock pulse width low iclk 9 C ns 7 ti_s input setup time to iclk 6 C ns 8 ti_h input hold to iclk 2 C ns 9 trwh reset pulse width high 50 C ns 10 twk wake-up time after reset (used for ram initialization during microprocessor con?guration access) 1280 2560 C C iclk cycles with dvalidin = high oclk cycles 11 ttdly delay from tn C 20 ns
pin descriptions and lists 6-5 6.2 pin descriptions and lists the following subsections provide descriptions for the electrical pins, as well as numerical and alphabetic listings of all L64777 pins. 6.2.1 L64777 electrical pin descriptions table 6.5 summarizes the electrical properties of the pins on the L64777. the table provides the signal types for both output and input pins, and the drive capacity for outputs. table 6.5 L64777 pin description summary mnemonic description type drive (ma) active avdd1 supply for dac analog input C C avdd2 supply for dac analog input C C avss1 analog supply for dac analog input C C avss2 supply for dac analog input C C comp1 compensation output for dac analog output C C comp2 compensation output for dac analog output C C dig_i[9:0] digital i output output 4 high dig_q[9:0] digital q output output 4 high din[7:0] data input ttl input C high dvalidin data enable input ttl input C high errorin error flag input ttl input C low fifoalarm fifo alarm output output 4 high firstout beginning of sequence output 4 high fstartin frame start input ttl input C high fstartout frame start output output 4 high
6-6 speci?cations ftmode[2:0] functional test mode input w/pulldown C high gnd ground analog C C iclk input clock ttl input C low/ high iddtn idd test ttl input w/pullup Clow int_n interrupt request open drain, driving low 4low iref1 reference current input analog input C C iref2 reference current input analog input C C nt_out nand tree output 4 high oclk vco clock output or external clock input bidirectional C low/ high pclk clock input for pll mode 2 ttl input C high pll_mode[1:0] select pll mode input w/pulldown C high pll_out_cs pll current source 3-state current source 4 3-state qam_i positive dac output i channel analog output C C qam_in negative dac output i channel analog output C C qam_q positive dac output q channel analog output C C qam_qn negative dac output q channel analog output C C reset_n chip reset ttl input C low sb_base[1:0] serial bus base address selector input w/pulldown C high table 6.5 L64777 pin description summary (cont.) mnemonic description type drive (ma) active
pin descriptions and lists 6-7 scan_enable scan enable ttl input w/pulldown C high scl serial control line input (5 v-tolerant) 4 high sclk symbol clock output output 4 low/ high sda serial data access bidirectional (5 v-tolerant) 4 open- drain sstartin sequence start input ttl input C high syncok sync detection flag output 4 high tck jtag test clock ttl input w/pulldown C+ 1 tdi jtag test data in ttl input w/pulldown C high tdo jtag test data out output 4 high tms jtag test mode select ttl input w/pulldown C high tnn 3-state mode ttl input w/pullup Clow trstn jtag test reset ttl input w/pulldown Clow vddx_i supply for digital dac part analog input C C vddx_q supply for digital dac part analog input C C vref_i voltage reference analog C C vref_q voltage reference analog C C 1. also 5 v compatible. table 6.5 L64777 pin description summary (cont.) mnemonic description type drive (ma) active
6-8 speci?cations 6.2.2 numerical pin list for the L64777 table 6.6 L64777 numerical pin list vdd 91 vss 92 nt_out 93 vss 94 scan_enable 95 ftmode.0 96 ftmode.1 97 ftmode.2 98 sb_base.0 99 sb+base.1 100 vss 101 pclk 102 vss 103 vdd 104 sclk 105 dig_i.0 106 dig_i.1 107 dig_i.2 108 dig_i.3 109 dig_i.4 110 vdd 111 dig_i.5 112 dig_i.6 113 dig_i.7 114 dig_i.8 115 dig_i.9 116 vdd 117 vss 118 scl 119 sda 120 signal pin signal pin vdd 1 vss 2 qam_i 3 qam_in 4 avdd1 5 iref1 6 comp1 7 vref_i 8 avss 9 vddx_i 10 vddx_q 11 avss2 12 vref_q 13 comp2 14 iref2 15 avdd2 16 qam_qn 17 qam_q 18 nc 19 gnd 20 nc 21 nc 22 nc 23 nc 24 nc 25 vss 26 pll_out_cs 27 vdd 28 vdd 29 nc 30 pll_mode.0 31 pll_mode.1 32 iddtn 33 tn 34 reset_n 35 vss 36 dig_q.0 37 dig_q.1 38 dig_q.2 39 dig_q.3 40 dig_q.4 41 vss 42 vdd 43 dig_q.5 44 dig_q.6 45 dig_q.7 46 dig_q.8 47 dig_q.9 48 vss 49 vss 50 vdd 51 oclk 52 vdd 53 vss 54 vss 55 tck 56 tdi 57 tms 58 vss 59 vdd 60 trstn 61 vdd 62 tdo 63 int_n 64 vss 65 vdd 66 fifoalarm 67 firstout 68 syncok 69 fstartout 70 vss 71 vdd 72 din.7 73 din.6 74 din.5 75 din.4 76 vdd 77 vss 78 vss 79 iclk 80 din.3 81 din.2 82 din.1 83 din.0 84 vss 85 vdd 86 dvalidin 87 errorin 88 fstartin 89 sstartin 90 signal pin signal pin 1. nc pins are not connected.
pin descriptions and lists 6-9 6.2.3 alphabetic pin list for the L64777 table 6.7 L64777 alphabetical pin list vdd77 vdd86 vdd91 vdd 104 vdd 111 vdd 117 vdd 62 vddx_i 10 vddx_q 11 vref_i 8 vref_q 13 vss 2 vss 26 vss 36 vss 42 vss 49 vss 50 vss 54 vss 55 vss 59 vss 65 vss 71 vss 78 vss 79 vss 85 vss 92 vss 94 vss 101 vss 103 vss 118 signal pin signal pin avdd1 5 avdd2 16 avss 9 avss2 12 comp1 7 comp2 14 dig_i.0 106 dig_i.1 107 dig_i.2 108 dig_i.3 109 dig_i.4 110 dig_i.5 112 dig_i.6 113 dig_i.7 114 dig_i.8 115 dig_i.9 116 dig_q.0 37 dig_q.1 38 dig_q.2 39 dig_q.3 40 dig_q.4 41 dig_q.5 44 dig_q.6 45 dig_q.7 46 dig_q.8 47 dig_q.9 48 din.0 84 din.1 83 din.2 82 din.3 81 din.4 76 din.5 75 din.6 74 din.7 73 dvalidin 87 errorin 88 fifoalarm 67 firstout 68 fstartin 89 fstartout 70 ftmode.0 96 ftmode.1 97 ftmode.2 98 gnd 20 iclk 80 iddtn 33 int_n 64 iref1 6 iref2 15 nc 22 nc 30 nc 21 nc 19 nc 23 nc 24 nc 25 nt_out 93 oclk 52 pclk 102 pll_mode.0 31 pll_mode.132 pll_out_cs 27 qam_i 3 qam_in 4 qam_q 18 qam_qn 17 reset_n 35 sb+base.1 100 sb_base.0 99 scan_enable 95 scl 119 sclk 105 sda 120 sstartin 90 syncok 69 tck 56 tdi 57 tdo 63 tms 58 tn 34 trstn 61 vdd 1 vdd 28 vdd 29 vdd 43 vdd 51 vdd 53 vdd 60 vdd 66 vdd 72 signal pin signal pin 1. nc pins are not connected.
6-10 speci?cations 6.3 package pinout figure 6.4 package 120-pin pqfp pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 vdd vss tms tdi tck vss vss vdd oclk vdd vss vss dig_q.9 dig_q.8 dig_q.7 dig_q.6 dig_q.5 vdd vss dig_q.4 dig_q.3 dig_q.2 dig_q.1 dig_q.0 vss reset_n tn iddtn pll_mode.1 pll_mode.0 sstartin fstartin errorin dvalidin vdd vss din.0 din.1 din.2 din.3 iclk vss vss vdd din.4 din.5 din.6 din.7 vdd vss fstartout syncok firstout fifoalarm vdd vss int_n tdo vdd trstn vdd vss nt_out vss scan_enable ftmode.0 ftmode.1 ftmode.2 sb_base.0 sb_base.1 vss pclk vss vdd sclk dig_i.0 dig_i.1 dig_i.2 dig_i.3 dig_i.4 dig_i.5 dig_i.6 dig_i.7 dig_i.8 dig_i.9 vdd vss scl sda vdd vss qam_i qam_in avdd1 iref1 comp1 vref_i avss1 vddx_i vddx_q avss2 vref_q comp2 iref2 avdd2 qam_qn qam_q nc gnd nc nc nc nc nc vss pll_out_cs vdd vdd nc top view L64777 vdd
package pinout 6-11 figure 6.5 provides a mechanical drawing of the 120-pin pqfp for the L64777. figure 6.5 120-pin pqfp (pe) mechanical drawing impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code pe.
6-12 speci?cations figure 6.5 120-pin pqfp (pe) mechanical drawing (cont.) impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code pe.
L64777 dvb qam modulator technical manual a-1 appendix a programming the L64777 in serial host interface mode this appendix discusses how to program the L64777 internal registers and data tables in serial host interface mode. this chapter is intended primarily for system programmers who are developing software drivers using the serial bus. this appendix contains the following sections: section a.1, serial bus protocol overview, page a-1, provides a high-level overview of the serial bus protocol. section a.2, programming the slave address using the serial bus interface, page a-4, shows how the slave address is formed and transmitted. section a.3, write cycle using the serial bus interface, page a-4, shows an example of a serial bus write cycle. section a.4, read cycle using the serial bus interface, page a-5, shows an example of a serial bus read cycle. section a.5, limitations, page a-7, shows the limitations of the L64777 a.1 serial bus protocol overview the multimaster serial bus interface has two 1-bit linessda (serial data) and scl (serial clock)that are connected to the bus as shown in figure a.1. external pullup resistors hold the bus at a logic 1 value when the bus is not in operation.
a-2 programming the L64777 in serial host interface mode figure a.1 quick overview of the serial bus at the serial interface, data transfers on the sda pin are synchronized to a serial clock input on the scl line. the serial data clock can have a maximum frequency of 400 khz. the pins sb_base[1:0] input the two lsbs of the slave address required by the serial bus protocol. the slave address de?nition is shown below: the bus master always generates the clock and cycle start and stop conditions. figure a.2 gives an overview of the read and write cycles using the serial bus protocol. 7-bit slave address for L64777 serial bus 1 1 0 1 0 sb_base1 sb_base0 scl sda 5 v serial bus compliant device serial bus compliant device
serial bus protocol overview a-3 figure a.2 serial bus write/read cycle start stop scl sda condition condition r/w master-transmitter, slave-receiver ack cycle: slave master-transmitter, slave-receiver write cycle bit7 bit6 bit5 bit3 bit2 bit1 bit0 bit4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 (master transmits slave address) (master transmits data to slave) ack cycle: slave sda r/w master-transmitter, slave-receiver ack cycle: slave master-receiver, slave-transmitter read cycle (burst) bit7 bit6 bit5 bit3 bit2 bit1 bit0 bit4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 (master transmits slave address) (slave transmits data to master) ack cycle: master sda r/w master-transmitter, slave-receiver ack cycle: slave master-receiver, slave-transmitter single-read cycle bit7 bit6 bit5 bit3 bit2 bit1 bit0 bit4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 (master transmits slave address) (slave transmits data to master) ack cycle: master stop condition bit7 start condition: the master (which drives the scl) indicates the start of a cycle by pulling sda to low when scl is high. stop condition: the master (which drives the scl) indicates the end of a cycle by releasing sda to high when scl is high. data transfer: all data changes on the sda line happen only when clock is low, except for the special cases outlined above to indicate cycle start/stop. acknowledge: the receiver always generates the acknowledge. in the case of a single read, the master-receiver does not generate an ack so that it can generate the stop condition (as indicated above).
a-4 programming the L64777 in serial host interface mode a.2 programming the slave address using the serial bus interface a general call (master does a start condition followed by eight 0s) address is used to address every device on the serial bus. any device that requires information to be supplied through this general call structure must acknowledge the cycle. the second byte has the following meaning when its lsb is 0 (see figure a.3): C 0b0000 0110 (0x6): reset and write the programmable part of the slave address by hardware from the sb_base pins. figure a.3 general call structure a.3 write cycle using the serial bus interface figure a.4 shows the timing for a burst, or a single-write cycle. the following cycles must take place for a write cycle: 1. the master starts the cycle with the start condition. 2. the master transmits the 7-bit slave address. 3. the master transmits an 8th bit (the r/w bit) = 0 to indicate a write cycle. 4. the addressed slave acknowledges the reception of the slave address by driving sda low in the ack cycle. 5. the master sends the 8-bit group 0 address (0x0) to indicate that the address programming register (apr) is to be loaded. (the master accesses group 0 only to load the apr.) 6. the master then sends the 8-bit data, which initializes the address pointer register (apr0). 0 000 00 00 x a xx x x x ax0 s general call address. s: start condition a: acknowledge cycle
read cycle using the serial bus interface a-5 7. the master generates another start condition. 8. the master repeats steps 2C7 to address the appropriate group and write 1 or more data bytes. 9. the master terminates the cycle by issuing a stop condition. figure a.4 burst write to slave (master-transmitter, slave-receiver) a.4 read cycle using the serial bus interface figure a.5 shows the timing for a burst, or a single read cycle. the following cycles must take place for a read cycle: 1. the master starts the cycle by issuing a start condition. 2. the master transmits the 7-bit slave address. 3. the master sets the r/w bit = 0 to indicate a write cycle. 4. the addressed slave acknowledges the reception of the slave address by driving sda low in the ack cycle. 5. the master sends the 8-bit group 0 address (0x0) to indicate that the apr is to be loaded. (the master accesses group 0 only to load the apr.) start stop scl sda condition condition bit 7 bit 6 bit 5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 r/w ack (slave) bit 0 7-bit slave address 8-bit group ack (slave) 2 3 1 ack (slave) address 8-bit data start condition 7 4 5 6 7-bit slave address ack (slave) ack (slave) ack (slave) ack (slave) 8-bit group address 8-bit data 8-bit data 9 8 sda
a-6 programming the L64777 in serial host interface mode 6. the master then sends the 8-bit data, which initializes the base pointer (apr0/1). 7. the master repeats the start condition. 8. the master transmits the 7-bit slave address. 9. the master sets the r/w bit = 0 to indicate a write cycle. 10. the addressed slave acknowledges the reception by driving sda low in the ack cycle. 11. the master transmits the number of the group that it wishes to read, which the slave acknowledges. 12. the master issues another start condition. 13. the master transmits the 7-bit slave address. 14. the master sets the r/w bit = 1 to indicate a read cycle. 15. the slave drives sda low to acknowledge. 16. the slave starts transmitting the data, msb ?rst. 17. the master has to provide the acknowledge by driving sda low during the ack cycle. 18. in the case of a single read, the master does not drive sda low during the ack cycle after reception of the ?rst byte. the slave responds to this by relinquishing control of the bus and waiting for the master to issue a stop condition. for burst reads, the master drives sda low for each byte it receives during the ack cycle, except for the last byte. 19. the master terminates the cycle by issuing a stop condition.
limitations a-7 figure a.5 single read from slave a.5 limitations you can access the internal registers either in bursts or single-byte operation. you must access the status registers 12 and 13 as single-byte read or write. after a stop condition, the user must program the apr to the desired next access address. do not rely on the expected location after the last access. start stop scl sda condition condition bit 7 bit 6 bit 5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 r/w ack (slave) bit 0 7-bit slave address 8-bit group ack (slave) 2 3 1 ack (slave) address 8-bit data start condition 7 4 7-bit slave address ack (slave) ack (slave) ack (master) 8-bit group address 19 8 sda r/w 9 10 11 ack (slave) 7-bit slave address r/w 12 13 14 15 18 8-bit data 16 17 start condition 5 6
a-8 programming the L64777 in serial host interface mode
L64777 dvb qam modulator technical manual b-1 appendix b pll divider settings and l64724/34 connection this appendix lists the pll divider settings for typical applications. it also describes the L64777 connection to the l64724 and contains the following sections: section b.1, overview, page b-1 section b.2, pll driver settings for typical applications, page b-2 section b.3, connecting the L64777 to the lsi logic l64724, page b-3 b.1 overview the qam modulator is the last stage in a digital catv transmitter system. figure b.1 shows a block diagram of a typical catv transmitter. figure b.1 catv block diagram video mpeg-2 qam mixer satellite transport decoder modulator rf source receiver power ampli?er to catv antenna source qam mixer modulator rf source power ampli?er to catv
b-2 pll divider settings and l64724/34 connection the qam modulator is programmed for its con?guration and operational modes through the serial microprocessor interface. the L64777 synchronizes with the input data, derives the operating clock (based on the operational mode), carries out clock conversion with appropriate fifo management, inserts the sync and error ?ags, and performs scrambling, rs encoding, and convolutional interleaving. signal frequencies at the symbol clock (sclk) and operating clock (oclk) outputs of the L64777 indicate appropriate locking of the internal timing system with respect to the incoming data rates when the input is from an mpeg source or the l64724 satellite receiver. the relationship among the sclk, oclk, and input data rate is described in the following subsections. if the same serial host controls both the l64724 and the L64777, hold the L64777 in reset until the l64724 pll has been programmed. b.2 pll driver settings for typical applications table b.1 lists the L64777s pll driver settings for mode 1. note that the above settings assume a block length of 204 bytes with 16 invalid bytes and ts is the effective input rate attained, considering the number of cycles with valid data. table b.1 typical settings of cnt_i and cnt_o iclk in mhz qam mode ts rate in mbyte/s /mbit/s cnt_i (decimal) cnt_o (decimal) frequency at phase comparator in mhz oclk in mhz 7.32 256 6.75/54.0 8 32 0.92 29.30 5.17 64 4.76/38.1 6 32 0.87 27.56 4.33 32 3.99/31.9 5 32 0.87 27.69 3.42 16 3.15/25.2 4 32 0.86 27.34
connecting the L64777 to the lsi logic l64724 b-3 b.3 connecting the L64777 to the lsi logic l64724 the L64777 can be connected to the satellite receiver device l64724. the l64724 uses an interpolation-based digital receiver. thus, it outputs a transport-rate byte clock with the granularity of the l64724 internal processing clock, pclk. see the lsi logic l64724 satellite receiver technical manual (april 2000). a digital nco generates this byte clock, which consists of clock cycles having a length of k or k + 1 pclk cycles. usually, the rate of the byte clock is exactly that of the received transport stream rate. to ease interfacing, the l64724 supports two modes of byte-clock generation. mode 2 of the synchronous parallel interface (spi) is best suited for interconnection with L64777. in this mode, the l64724 outputs 204-byte clock cycles, together with an indication for the 188 valid data bytes. connect the byte clock to the iclk input of the L64777, as a reference for generating the output sampling rate (oclk); and connect the pclk output of the l64724 to the pclk input of L64777. to keep the loop bandwidth as low as possible, L64777 provides a digital interpolation scheme and an nco to lock to the byte clock in pll mode 2. figure b.2 provides a simpli?ed illustration of the signals between the l64724 and the L64777. figure b.2 signals between the l64724 and L64777 l64724 L64777 pclk pclk din(7:0) dvalidin iclk co(7:0) dvalidout bclkout
b-4 pll divider settings and l64724/34 connection when the input to the L64777 is from the l64724 for a satellite of selected center frequency and baud rate, the parameters to be programmed into the L64777 for 64 qam are: operational mode = nco mode (mode 2) block length = 188 bytes gap = 16 bytes i-counter = 6 (0x6) o-counter = 32 (0x20) after synchronization: oclk = baud rate x 2 x 3/4 x oversampling x 1/(symbol size) sclk = oclk/4 where: oversampling = 4 symbol size = 6 for qam mode of 64 (log of qam level to base 2) note that the pll_set bit (register 1) must be set before downloading any counter parameters, and it must be cleared after completion. this applies to mode 2 programming.
L64777 dvb qam modulator technical manual c-1 appendix c monitoring device internal signals the programming of the test register (14) allows monitoring of the devices internal signals. depending on the programming of the test register bits (register 15), the following signals are observable on the dig_q[9:0] pins: test[3:0] 0b0000: nyquist ?lter output or interpolator output (normal operation) 0b0001: fifo output 0b0010: scrambler output 0b0011: rs encoder output 0b0100: interleaver output 0b0101: m-tuple output 0b0110: mapper output 0b0111: n/a 0b1000: interpolator control 0b1001: nco step bit [23:16] on dig_q[7:0] 0b1010: nco step bit [15:8] on dig_q[7:0] 0b1011: nco step bit [7:0] on dig_q[7:0] 0b1100: virtual fifo content 0b1101: value reserved; do not program 0b1110: value reserved; do not program 0b1111: value reserved; do not program test.4: set to 1 for power-down mode; after reset, this is 0 test.5: set to 1 for power-down mode; after reset, this is 0 test.6: set to 1 for power-down mode; after reset, this is 0
c-2 monitoring device internal signals
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u.s. distributors by state a. e. avnet electronics http://www.hh.avnet.com b. m. bell microproducts, inc. (for habs) http://www.bellmicro.com i. e. insight electronics http://www.insight-electronics.com w. e. wyle electronics http://www.wyle.com alabama daphne i. e. tel: 334.626.6190 huntsville a. e. tel: 256.837.8700 b. m. tel: 256.705.3559 i. e. tel: 256.830.1222 w. e. tel: 800.964.9953 alaska a. e. tel: 800.332.8638 arizona phoenix a. e. tel: 480.736.7000 b. m. tel: 602.267.9551 w. e. tel: 800.528.4040 tempe i. e. tel: 480.829.1800 tucson a. e. tel: 520.742.0515 arkansas w. e. tel: 972.235.9953 california agoura hills b. m. tel: 818.865.0266 granite bay b. m. tel: 916.523.7047 irvine a. e. tel: 949.789.4100 b. m. tel: 949.470.2900 i. e. tel: 949.727.3291 w. e. tel: 800.626.9953 los angeles a. e. tel: 818.594.0404 w. e. tel: 800.288.9953 sacramento a. e. tel: 916.632.4500 w. e. tel: 800.627.9953 san diego a. e. tel: 858.385.7500 b. m. tel: 858.597.3010 i. e. tel: 800.677.6011 w. e. tel: 800.829.9953 san jose a. e. tel: 408.435.3500 b. m. tel: 408.436.0881 i. e. tel: 408.952.7000 santa clara w. e. tel: 800.866.9953 woodland hills a. e. tel: 818.594.0404 westlake village i. e. tel: 818.707.2101 colorado denver a. e. tel: 303.790.1662 b. m. tel: 303.846.3065 w. e. tel: 800.933.9953 englewood i. e. tel: 303.649.1800 idaho springs b. m. tel: 303.567.0703 connecticut cheshire a. e. tel: 203.271.5700 i. e. tel: 203.272.5843 wallingford w. e. tel: 800.605.9953 delaware north/south a. e. tel: 800.526.4812 tel: 800.638.5988 b. m. tel: 302.328.8968 w. e. tel: 856.439.9110 florida altamonte springs b. m. tel: 407.682.1199 i. e. tel: 407.834.6310 boca raton i. e. tel: 561.997.2540 bonita springs b. m. tel: 941.498.6011 clearwater i. e. tel: 727.524.8850 fort lauderdale a. e. tel: 954.484.5482 w. e. tel: 800.568.9953 miami b. m. tel: 305.477.6406 orlando a. e. tel: 407.657.3300 w. e. tel: 407.740.7450 tampa w. e. tel: 800.395.9953 st. petersburg a. e. tel: 727.507.5000 georgia atlanta a. e. tel: 770.623.4400 b. m. tel: 770.980.4922 w. e. tel: 800.876.9953 duluth i. e. tel: 678.584.0812 hawaii a. e. tel: 800.851.2282 idaho a. e. tel: 801.365.3800 w. e. tel: 801.974.9953 illinois north/south a. e. tel: 847.797.7300 tel: 314.291.5350 chicago b. m. tel: 847.413.8530 w. e. tel: 800.853.9953 schaumburg i. e. tel: 847.885.9700 indiana fort wayne i. e. tel: 219.436.4250 w. e. tel: 888.358.9953 indianapolis a. e. tel: 317.575.3500 iowa w. e. tel: 612.853.2280 cedar rapids a. e. tel: 319.393.0033 kansas w. e. tel: 303.457.9953 kansas city a. e. tel: 913.663.7900 lenexa i. e. tel: 913.492.0408 kentucky w. e. tel: 937.436.9953 central/northern/ western a. e. tel: 800.984.9503 tel: 800.767.0329 tel: 800.829.0146 louisiana w. e. tel: 713.854.9953 north/south a. e. tel: 800.231.0253 tel: 800.231.5775 maine a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 maryland baltimore a. e. tel: 410.720.3400 w. e. tel: 800.863.9953 columbia b. m. tel: 800.673.7461 i. e. tel: 410.381.3131 massachusetts boston a. e. tel: 978.532.9808 w. e. tel: 800.444.9953 burlington i. e. tel: 781.270.9400 marlborough b. m. tel: 800.673.7459 woburn b. m. tel: 800.552.4305 michigan brighton i. e. tel: 810.229.7710 detroit a. e. tel: 734.416.5800 w. e. tel: 888.318.9953 clarkston b. m. tel: 877.922.9363 minnesota champlin b. m. tel: 800.557.2566 eden prairie b. m. tel: 800.255.1469 minneapolis a. e. tel: 612.346.3000 w. e. tel: 800.860.9953 st. louis park i. e. tel: 612.525.9999 mississippi a. e. tel: 800.633.2918 w. e. tel: 256.830.1119 missouri w. e. tel: 630.620.0969 st. louis a. e. tel: 314.291.5350 i. e. tel: 314.872.2182 montana a. e. tel: 800.526.1741 w. e. tel: 801.974.9953 nebraska a. e. tel: 800.332.4375 w. e. tel: 303.457.9953 nevada las vegas a. e. tel: 800.528.8471 w. e. tel: 702.765.7117 new hampshire a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 new jersey north/south a. e. tel: 201.515.1641 tel: 609.222.6400 mt. laurel i. e. tel: 856.222.9566 pine brook b. m. tel: 973.244.9668 w. e. tel: 800.862.9953 parsippany i. e. tel: 973.299.4425 wayne w. e. tel: 973.237.9010 new mexico w. e. tel: 480.804.7000 albuquerque a. e. tel: 505.293.5119
u.s. distributors by state (continued) new york hauppauge i. e. tel: 516.761.0960 long island a. e. tel: 516.434.7400 w. e. tel: 800.861.9953 rochester a. e. tel: 716.475.9130 i. e. tel: 716.242.7790 w. e. tel: 800.319.9953 smithtown b. m. tel: 800.543.2008 syracuse a. e. tel: 315.449.4927 north carolina raleigh a. e. tel: 919.859.9159 i. e. tel: 919.873.9922 w. e. tel: 800.560.9953 north dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 ohio cleveland a. e. tel: 216.498.1100 w. e. tel: 800.763.9953 dayton a. e. tel: 614.888.3313 i. e. tel: 937.253.7501 w. e. tel: 800.575.9953 strongsville b. m. tel: 440.238.0404 valley view i. e. tel: 216.520.4333 oklahoma w. e. tel: 972.235.9953 tulsa a. e. tel: 918.459.6000 i. e. tel: 918.665.4664 oregon beaverton b. m. tel: 503.524.1075 i. e. tel: 503.644.3300 portland a. e. tel: 503.526.6200 w. e. tel: 800.879.9953 pennsylvania mercer i. e. tel: 412.662.2707 philadelphia a. e. tel: 800.526.4812 b. m. tel: 877.351.2355 w. e. tel: 800.871.9953 pittsburgh a. e. tel: 412.281.4150 w. e. tel: 440.248.9996 rhode island a. e. 800.272.9255 w. e. tel: 781.271.9953 south carolina a. e. tel: 919.872.0712 w. e. tel: 919.469.1502 south dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 tennessee w. e. tel: 256.830.1119 east/west a. e. tel: 800.241.8182 tel: 800.633.2918 texas arlington b. m. tel: 817.417.5993 austin a. e. tel: 512.219.3700 b. m. tel: 512.258.0725 i. e. tel: 512.719.3090 w. e. tel: 800.365.9953 dallas a. e. tel: 214.553.4300 b. m. tel: 972.783.4191 w. e. tel: 800.955.9953 el paso a. e. tel: 800.526.9238 houston a. e. tel: 713.781.6100 b. m. tel: 713.917.0663 w. e. tel: 800.888.9953 richardson i. e. tel: 972.783.0800 rio grande valley a. e. tel: 210.412.2047 stafford i. e. tel: 281.277.8200 utah centerville b. m. tel: 801.295.3900 murray i. e. tel: 801.288.9001 salt lake city a. e. tel: 801.365.3800 w. e. tel: 800.477.9953 vermont a. e. tel: 800.272.9255 w. e. tel: 716.334.5970 virginia a. e. tel: 800.638.5988 w. e. tel: 301.604.8488 haymarket b. m. tel: 703.754.3399 spring?eld b. m. tel: 703.644.9045 washington kirkland i. e. tel: 425.820.8100 maple valley b. m. tel: 206.223.0080 seattle a. e. tel: 425.882.7000 w. e. tel: 800.248.9953 west virginia a. e. tel: 800.638.5988 wisconsin milwaukee a. e. tel: 414.513.1500 w. e. tel: 800.867.9953 wauwatosa i. e. tel: 414.258.5338 wyoming a. e. tel: 800.332.9326 w. e. tel: 801.974.9953
sales of?ces and design resource centers lsi logic corporation corporate headquarters 1551 mccarthy blvd milpitas ca 95035 tel: 408.433.8000 fax: 408.433.8989 north america california irvine 18301 von karman ave suite 900 irvine, ca 92612 tel: 949.809.4600 fax: 949.809.4444 pleasanton design center 5050 hopyard road, 3rd floor suite 300 pleasanton, ca 94588 tel: 925.730.8800 fax: 925.730.8700 san diego 7585 ronson road suite 100 san diego, ca 92111 tel: 858.467.6981 fax: 858.496.0548 silicon valley 1551 mccarthy blvd sales of?ce m/s c-500 milpitas, ca 95035 tel: 408.433.8000 fax: 408.954.3353 design center m/s c-410 tel: 408.433.8000 fax: 408.433.7695 wireless design center 11452 el camino real suite 210 san diego, ca 92130 tel: 858.350.5560 fax: 858.350.0171 colorado boulder 4940 pearl east circle suite 201 boulder, co 80301 tel: 303.447.3800 fax: 303.541.0641 colorado springs 4420 arrowswest drive colorado springs, co 80907 tel: 719.533.7000 fax: 719.533.7020 fort collins 2001 dan?eld court fort collins, co 80525 tel: 970.223.5100 fax: 970.206.5549 florida boca raton 2255 glades road suite 324a boca raton, fl 33431 tel: 561.989.3236 fax: 561.989.3237 georgia alpharetta 2475 north winds parkway suite 200 alpharetta, ga 30004 tel: 770.753.6146 fax: 770.753.6147 illinois oakbrook terrace two mid american plaza suite 800 oakbrook terrace, il 60181 tel: 630.954.2234 fax: 630.954.2235 kentucky bowling green 1262 chestnut street bowling green, ky 42101 tel: 270.793.0010 fax: 270.793.0040 maryland bethesda 6903 rockledge drive suite 230 bethesda, md 20817 tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham 200 west street waltham, ma 02451 tel: 781.890.0180 fax: 781.890.6158 burlington - mint technology 77 south bedford street burlington, ma 01803 tel: 781.685.3800 fax: 781.685.3801 minnesota minneapolis 8300 norman center drive suite 730 minneapolis, mn 55437 tel: 612.921.8300 fax: 612.921.8399 new jersey red bank 125 half mile road suite 200 red bank, nj 07701 tel: 732.933.2656 fax: 732.933.2643 cherry hill - mint technology 215 longstone drive cherry hill, nj 08003 tel: 856.489.5530 fax: 856.489.5531 new york fairport 550 willowbrook of?ce park fairport, ny 14450 tel: 716.218.0020 fax: 716.218.9010 north carolina raleigh phase ii 4601 six forks road suite 528 raleigh, nc 27609 tel: 919.785.4520 fax: 919.783.8909 oregon beaverton 15455 nw greenbrier parkway suite 235 beaverton, or 97006 tel: 503.645.0589 fax: 503.645.6612 texas austin 9020 capital of tx highway north building 1 suite 150 austin, tx 78759 tel: 512.388.7294 fax: 512.388.4171 plano 500 north central expressway suite 440 plano, tx 75074 tel: 972.244.5000 fax: 972.244.5001 houston 20405 state highway 249 suite 450 houston, tx 77070 tel: 281.379.7800 fax: 281.379.7818 canada ontario ottawa 260 hearst way suite 400 kanata, on k2l 3h1 tel: 613.592.1263 fax: 613.592.3253 international france paris lsi logic s.a. immeuble europa 53 bis avenue de l'europe b.p. 139 78148 velizy-villacoublay cedex, paris tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany munich lsi logic gmbh orleansstrasse 4 81669 munich tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart mittlerer pfad 4 d-70499 stuttgart tel: 49.711.13.96.90 fax: 49.711.86.61.428 italy milan lsi logic s.p.a. centro direzionale colleoni palazzo orione ingresso 1 20041 agrate brianza, milano tel: 39.039.687371 fax: 39.039.6057867 japan tokyo lsi logic k.k. rivage-shinagawa bldg. 14f 4-1-8 kounan minato-ku, tokyo 108-0075 tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka crystal tower 14f 1-2-27 shiromi chuo-ku, osaka 540-6014 tel: 81.6.947.5281 fax: 81.6.947.5287
sales of?ces and design resource centers (continued) korea seoul lsi logic corporation of korea ltd 10th fl., haesung 1 bldg. 942, daechi-dong, kangnam-ku, seoul, 135-283 tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands eindhoven lsi logic europe ltd world trade center eindhoven building rijder bogert 26 5612 lz eindhoven tel: 31.40.265.3580 fax: 31.40.296.2109 singapore singapore lsi logic pte ltd 7 temasek boulevard #28-02 suntec tower one singapore 038987 tel: 65.334.9061 fax: 65.334.4749 sweden stockholm lsi logic ab finlandsgatan 14 164 74 kista tel: 46.8.444.15.00 fax: 46.8.750.66.47 taiwan taipei lsi logic asia, inc. taiwan branch 10/f 156 min sheng e. road section 3 taipei, taiwan r.o.c. tel: 886.2.2718.7828 fax: 886.2.2718.8869 united kingdom bracknell lsi logic europe ltd greenwood house london road bracknell, berkshire rg12 2ub tel: 44.1344.426544 fax: 44.1344.481039 sales of?ces with design resource centers
international distributors australia new south wales reptechnic pty ltd 3/36 bydown street neutral bay, nsw 2089 tel: 612.9953.9844 fax: 612.9953.9683 belgium acal nv/sa lozenberg 4 1932 zaventem tel: 32.2.7205983 fax: 32.2.7251014 china beijing lsi logic international services inc. beijing representative of?ce room 708 canway building 66 nan li shi lu xicheng district beijing 100045, china tel: 86.10.6804.2534 to 38 fax: 86.10.6804.2521 france rungis cedex azzurri technology france 22 rue saarinen sillic 274 94578 rungis cedex tel: 33.1.41806310 fax: 33.1.41730340 germany haar ebv elektronik hans-pinsel str. 4 d-85540 haar tel: 49.89.4600980 fax: 49.89.46009840 munich avnet emg gmbh stahlgruberring 12 81829 munich tel: 49.89.45110102 fax: 49.89.42.27.75 wuennenberg-haaren peacock ag graf-zepplin-str 14 d-33181 wuennenberg-haaren tel: 49.2957.79.1692 fax: 49.2957.79.9341 hong kong hong kong avt industrial ltd unit 608 tower 1 cheung sha wan plaza 833 cheung sha wan road kowloon, hong kong tel: 852.2428.0008 fax: 852.2401.2105 serial system (hk) ltd 2301 nanyang plaza 57 hung to road, kwun tong kowloon, hong kong tel: 852.2995.7538 fax: 852.2950.0386 india bangalore spike technologies india private ltd 951, vijayalakshmi complex, 2nd floor, 24th main, j p nagar ii phase, bangalore, india 560078 tel: 91.80.664.5530 fax: 91.80.664.9748 israel tel aviv eastronics ltd 11 rozanis street p.o. box 39300 tel aviv 61392 tel: 972.3.6458777 fax: 972.3.6458666 japan tokyo daito electron sogo kojimachi no.3 bldg 1-6 kojimachi chiyoda-ku, tokyo 102-8730 tel: 81.3.3264.0326 fax: 81.3.3261.3984 global electronics corporation nichibei time24 bldg. 35 tansu-cho shinjuku-ku, tokyo 162-0833 tel: 81.3.3260.1411 fax: 81.3.3260.7100 technical center tel: 81.471.43.8200 marubeni solutions 1-26-20 higashi shibuya-ku, tokyo 150-0001 tel: 81.3.5778.8662 fax: 81.3.5778.8669 shinki electronics myuru daikanyama 3f 3-7-3 ebisu minami shibuya-ku, tokyo 150-0022 tel: 81.3.3760.3110 fax: 81.3.3760.3101 yokohama-city innotech 2-15-10 shin yokohama kohoku-ku yokohama-city, 222-8580 tel: 81.45.474.9037 fax: 81.45.474.9065 macnica corporation hakusan high-tech park 1-22-2 hadusan, midori-ku, yokohama-city, 226-8505 tel: 81.45.939.6140 fax: 81.45.939.6141 the netherlands eindhoven acal nederland b.v. beatrix de rijkweg 8 5657 eg eindhoven tel: 31.40.2.502602 fax: 31.40.2.510255 switzerland brugg lsi logic sulzer ag mattenstrasse 6a ch 2555 brugg tel: 41.32.3743232 fax: 41.32.3743233 taiwan taipei avnet-mercuries corporation, ltd 14f, no. 145, sec. 2, chien kuo n. road taipei, taiwan, r.o.c. tel: 886.2.2516.7303 fax: 886.2.2505.7391 lumax international corporation, ltd 7th fl., 52, sec. 3 nan-kang road taipei, taiwan, r.o.c. tel: 886.2.2788.3656 fax: 886.2.2788.3568 prospect technology corporation, ltd 4fl., no. 34, chu luen street taipei, taiwan, r.o.c. tel: 886.2.2721.9533 fax: 886.2.2773.3756 wintech microeletronics co., ltd 7f., no. 34, sec. 3, pateh road taipei, taiwan, r.o.c. tel: 886.2.2579.5858 fax: 886.2.2570.3123 united kingdom maidenhead azzurri technology ltd 16 grove park business estate waltham road white waltham maidenhead, berkshire sl6 3lw tel: 44.1628.826826 fax: 44.1628.829730 milton keynes ingram micro (uk) ltd garamonde drive wymbush milton keynes buckinghamshire mk8 8df tel: 44.1908.260422 swindon ebv elektronik 12 interface business park bincknoll lane wootton bassett, swindon, wiltshire sn4 8sy tel: 44.1793.849933 fax: 44.1793.859555 sales of?ces with design resource centers

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